EM78P350N
8-Bit Microprocessor with OTP ROM
Status
Operation
Binary Instruction
HEX
Mnemonic
Affected
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
1 00kk kkkk kkkk
1 01kk kkkk kkkk
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
06rr
06rr
06rr
06rr
07rr
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
1kkk
OR A,R
OR R,A
A ∨ VR → A
A ∨ VR → R
Z
Z
AND A,R A & R → A
AND R,A A & R → R
XOR A,R A ⊕ R → A
XOR R,A A ⊕ R → R
ADD A,R A + R → A
ADD R,A A + R → R
MOV A,R R → A
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
MOV R,R R → R
Z
COMA R /R → A
Z
COM R
INCA R
INC R
/R → R
Z
R+1 → A
Z
R+1 → R
Z
DJZA R
DJZ R
R-1 → A, skip if zero
None
None
C
R-1 → R, skip if zero
RRCA R
RRC R
RLCA R
RLC R
R(n) → A(n-1), R(0) → C, C → A(7)
R(n) → R(n-1), R(0) → C, C → R(7)
R(n) → A(n+1), R(7) → C, C → A(0)
R(n) → R(n+1), R(7) → C, C → R(0)
C
C
C
SWAPA R R(0-3) → A(4-7), R(4-7) → A(0-3)
SWAP R R(0-3) ↔ R(4-7)
None
None
None
None
None1
None2
None
None
None
None
JZA R
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
JMP k
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → SP, (Page, k ) → PC
(Page, k ) → PC
Product Specification (V 1.0) 09.14.2006
(This specification is subject to change without further notice)
• 89
ELAN [ ELAN MICROELECTRONICS CORP ]
