EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.13 Code Option
EM78P341N/342N/343N has two CODE option words and one Customer ID word that
are not part of the normal program memory.
Word 0
Word1
Word 2
Bit 12 ~ Bit 0
Bit 12 ~ Bit 0
Bit12 ~ Bit 0
6.13.1 Code Option Register (Word 0)
Word 0
Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LVR1 LVR0 TYPE1 TYPE0 CLKS ENWDTB OSC2 OSC1 OSC0 HLP
−
−
−
Bits 12~11 (LVR1 ~ LVR0): Low Voltage Reset enable bits
LVR1, LVR0
VDD Reset Level
VDD Release Level
11
10
01
00
NA (Power-on Reset) (Default)
2.7V
3.5V
4.0V
2.9V
3.7V
4.2V
Bits 10~9 (TYPE1 ~ TYPE0): Type selection for EM78P343N or EM78P342N or
EM78P341N or 108C.
TYPE 1, TYPE 0
VDD Reset Level
108C (8-pin)
00
01
10
11
EM78P341N (14-pin)
EM78P342N (18-pin)
EM78P343N (Default) (20-pin)
Bit 8 (CLKS):
Instruction period option bit
0 = two oscillator periods
1 = four oscillator periods (default)
Refer to Section 6.15 for Instruction Set
Bit 7 (ENWDTB): Watchdog timer enable bit
0 = Enable
1 = Disable (default)
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
