EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
When an interrupt is generated by the High time / Low time down counter underflow
(when enabled), the next instruction will be fetched from Addresses 012 and 015H
(High time and Low time respectively).
When an interrupt is generated by the Comparators (when enabled), the next
instruction will be fetched from Address 00FH (Comparator interrupt).
When an interrupt is generated by the Low Voltage Detect (when enabled), the next
instruction will be fetched from Address 021 (Low Voltage Detector interrupt).
Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4
registers are saved first by the hardware. If another interrupt occurs, the ACC, R3, and
R4 will be replaced by the new interrupt. After an interrupt service routine is completed,
the ACC, R3, and R4 registers are restored.
VCC
P
D
Q
IRQn
R
/IRQn
CLK
INT
_
Q
IRQm
C
L
RFRD
RF
ENI/DISI
P
IOD
Q
D
R
CLK
_
Q
IOCFWR
C
L
IOCF
/RESET
IOCFRD
RFWR
Fig. 6.9 Interrupt Input Circuit
Interrupt
occurs
Interrupt Sources
ENI/DISI
ACC
Stack ACC
R3
R4
Sack R3
Stack R4
RETI
Fig. 6.10 Interrupt Backup Diagram
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
