EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.6 Interrupt
The EM78P341N/342N/343N has six interrupts as listed below:
1. TCC, TCCA, TCCB, TCCC overflow interrupt
2. Port 5 Input Status Change Interrupt
3. External interrupt [(P60, /INT) pin]
4. Analog to Digital conversion completed
5. IR/PWM underflow interrupt
6. When the comparators status changes (not applicable to EM78P341N)
7. Low voltage detector interrupt
Before the Port 5 Input Status Change Interrupt is enabled, reading Port 5 (e.g. "MOV
R5,R5") is necessary. Each Port 5 pin will have this feature if its status changes. The
Port 5 Input Status Change Interrupt will wake up the EM78P341N/342N/343N from
sleep mode if it is enabled prior to going into sleep mode by executing SLEP instruction.
When wake up occurs, the controller will continue to execute program in-line if the global
interrupt is disabled. If enabled, the global interrupt will branch out to the interrupt vector
006H.
External interrupt equipped with digital noise rejection circuit (input pulse less than
system clock time) is eliminated as noise. However, under Low Crystal oscillator (LXT)
mode the noise rejection circuit will be disabled. Edge selection is possible with INTE
of CONT. When an interrupt is generated by the External interrupt (when enabled), the
next instruction will be fetched from address 003H. Refer to the Word 1 Bits 9 & 8
(Section 6.14.2, Code Option Register (Word 1)) for digital noise rejection definition.
RF and RE are the interrupt status register that records the interrupt requests in the
relative flags/bits. IOCF0 and IOCE0 are interrupt mask registers. The global interrupt
is enabled by the ENI instruction and is disabled by the DISI instruction. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine to avoid recursive interrupts.
The flag (except for the ICIF bit) in the Interrupt Status Register (RF) is set regardless of
the ENI execution. Note that the result of RF will be the logic AND of RF and IOCF0
(refer to figure below). The RETI instruction ends the interrupt routine and enables the
global interrupt (the ENI execution).
When an interrupt is generated by the Timer clock/counter (when enabled), the next
instruction will be fetched from Address 009, 018, 01B, and 01EH (TCC, TCCA, TCCB,
and TCCC respectively).
When an interrupt generated by the AD conversion is completed (when enabled), the
next instruction will be fetched from Address 00CH.
50 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
