EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.5.1.3 Controller Reset Block Diagram
VDD
D
Q
CLK
Oscillator
CLK
CLR
Power-on Reset
Voltage
Detector
ENWDTB
WDT Timeout
WDT
Reset
Setup time
/RESET
Fig. 6-8 Controller Reset Block Diagram
6.5.2 The T and P Status under Status (R3) Register
A reset condition is initiated by one of the following events:
1. Power-on reset
2. /RESET pin input "low"
3. WDT time-out (if enabled)
The values of RST, T, and P as listed in the table below, are used to check how the
processor wakes up.
Reset Type
RST
T
P
Power-on
0
0
0
0
0
1
1
*P
1
1
*P
0
/RESET during Operating mode
/RESET wake-up during SLEEP mode
WDT during Operating mode
0
1
WDT wake-up during SLEEP mode
Wake-up on pin change during SLEEP mode
0
0
1
0
*P: Previous status before reset
The following shows the events that may affect the status of T and P.
Event
RST
T
P
Power-on
0
*P
0
1
1
0
1
1
1
1
WDTC instruction
WDT time-out
SLEP instruction
*P
0
*P
1
Wake-up on pin changed during SLEEP mode
0
*P: Previous value before reset
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
• 49
ELAN [ ELAN MICROELECTRONICS CORP ]
