EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.1.13 RD (ADDATA1L: Converted Value of ADC)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-up Control Register)) is set.
RD is read only
6.1.14 RE (Interrupt Status 2 & Wake-up Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
/LVD
LVDIF
ADIF
CMPIF
ADWE
CMPWE
ICWE
LVDWE
NOTE
■ RE <5,4> can be cleared by instruction but cannot be set.
■ IOCE0 is the interrupt mask register.
■ Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 (/LVD):
Low voltage Detector state. This is a read only bit. When the VDD
pin voltage is lower than LVD voltage interrupt level (selected by
LVD1 and LVD0), this bit will be cleared.
0 = low voltage is detected
1 = low voltage is not detected or LVD function is disabled
Bit 6 (LVDIF):
Bit 5 (ADIF):
Low Voltage Detector interrupt flag
LVDIF is reset to “0” by software.
Interrupt flag for analog to digital conversion. Set when AD
conversion is completed. Reset by software.
0 = no interrupt occurs
1 = interrupt request
Bit 4 (CMPIF): Comparator interrupt flag. Set when a change occurs in the
Comparator output. Reset by software.
0 = no interrupt occurs
1 = interrupt request
Bit 3 (ADWE): ADC wake-up enable bit
0 = Disable ADC wake-up
1 = Enable ADC wake-up
When AD Conversion enters sleep mode, this bit must be set to
“Enable“.
16 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
