EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE
The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time.
If P53/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 “TS”
must be “0.”
The VREF/TCC/P54 Pin Priority is as follows:
P53/TCC/VREF Pin Priority
High
Medium
TCC
Low
P54
VREF
Bit 6 & Bit 5 (CKR1 & CKR0): The prescaler of ADC oscillator clock rate
00 = 1: 16 (default value)
01 = 1: 4
10 = 1: 64
11 = 1: 8
CPUS
CKR1:CKR0 Operation Mode Max. Operation Frequency
1
1
1
1
0
00
01
10
11
XX
Fosc/16
Fosc/4
4MHz
1MHz
16MHz
2MHz
-
Fosc/64
Fosc/8
Internal RC
Bit 4 (ADRUN): ADC starts to RUN.
1 = an AD conversion is started. This bit can be set by software
0 = Reset upon completion of the conversion. This bit cannot be
reset through software
Bit 3 (ADPD): ADC Power-down mode
1 = ADC is operating
0 = Switch off the resistor reference to save power even while the
CPU is operating
Bit 2 ~ Bit 0 (ADIS2 ~ADIS0): Analog Input Select
000 = ADIN0/P50
001 = ADIN1/P51
010 = ADIN2/P52
011 = ADIN3/P53
100 = ADIN0/P67
101 = ADIN1/P70
110 = ADIN2/P55
111 = ADIN3/P57
These bits can only be changed when the ADIF bit (see Section 6.1.14, RE (Interrupt
Status 2 & Wake-up Control Register)) and the ADRUN bit are both LOW.
14 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
