EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits
PST2
PST1
PST0
TCC Rate
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1
1
1
1:256
NOTE
Tcc timeout period [1/Fosc x prescaler x 256 (Tcc cnt) x 1 (CLK=2)]
Tcc timeout period [1/Fosc x prescaler x 256 (Tcc cnt) x 2 (CLK=4)]
6.2.3 IOC50 ~ IOC70 (I/O Port Control Register)
ꢀ
"1" puts the relative I/O pin into high impedance, while "0" defines the relative I/O
pin as output.
ꢀ
Only the lower 6 bits of IOC50 can be defined (this applies to EM78P259N only as
EM78P260N can use all the bits).
ꢀ
ꢀ
Only the lower 1 bits of IOC70 can be defined, the others bits are not available.
IOC50, IOC60, and IOC70 registers are all readable and writable
6.2.4 IOC80 (Comparator and TCCA Control Register)
7
6
5
4
3
2
1
0
–
–
CMPOUT
COS1
COS0
TCCAEN TCCATS TCCATE
NOTE
■ Bits 4 ~ 0 of the IOC80 register are both readable and writable.
■ Bit5 of the IOC80 register is readable only.
Bit 7 & Bit 6:
Not used
Bit 5 (CMPOUT): The result of the comparator output
This bit is readable only
Product Specification (V1.0) 06.16.2005
• 17
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
