EM78P259N/260N
8-Bit Microprocessor with OTP ROM
6.1.12 RC (ADDATA1H: Converted Value of ADC)
7
6
5
4
3
2
1
0
“0”
“0”
“0”
“0”
AD11
AD10
AD9
AD8
When the AD conversion is completed, the result is loaded into the ADDATA1H. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-Up Control Register)) is set.
RC is read only
6.1.13 RD (ADDATA1L: Converted Value of ADC)
7
6
5
4
3
2
1
0
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
When the AD conversion is completed, the result is loaded into the ADDATA1L. The
ADRUN bit is cleared, and the ADIF (see Section 6.1.14, RE (Interrupt Status 2 &
Wake-Up Control Register)) is set.
RD is read only
6.1.14 RE (Interrupt Status 2 & Wake-Up Control Register)
7
6
5
4
3
2
1
0
–
–
ADIF
CMPIF
ADWE
CMPWE
ICWE
-
NOTE
■ RE <5,4> can be cleared by instruction but cannot be set.
■ IOCE0 is the interrupt mask register.
■ Reading RE will result to "logic AND" of RE and IOCE0.
Bit 7 & Bit 6:
Bit 5 (ADIF):
Not used
Interrupt flag for analog to digital conversion. Set when AD
conversion is completed. Reset by software
0 = no interrupt occurs
1 = interrupt request
Bit 4 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of
Comparator. Reset by software.
0 = no interrupt occurs
1 = interrupt request
Bit 3 (ADWE): ADC wake-up enable bit
0 = Disable ADC wake-up
1 = Enable ADC wake-up
When AD Conversion enters sleep mode, this bit must be set to
“Enable“.
14 •
Product Specification (V1.0) 06.16.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
