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EM78P259NSO14J 参数 Datasheet PDF下载

EM78P259NSO14J图片预览
型号: EM78P259NSO14J
PDF下载: 下载PDF文件 查看货源
内容描述: [EM78Q153SN EM78P153SP EM78P153SN EM78156EH EM78156EP EM78156EM EM78156EKM EM78Q156ELP EM78Q156ELM EM78Q156ELKM EM78P156ELP EM78P156ELM EM78P156ELKM EM78P156NP EM78P156NM EM78447SH EM78447SAP EM78447SAM EM78447SAS EM78447SBP EM78447SBWM EM78Q447SH EM78Q447SAP EM78Q447SAM EM78Q447SBP EM78Q447SBWM EM78P447SAP EM78P447SAM EM78P447SAS EM78P447SBP EM78P447SBWM EM78Q257 EM78Q257AP EM78Q257AM EM78Q257BP EM78Q257BM EM78P257AP EM78P257AM EM78P257BP EM78P257BM EM78451H EM78451P EM78451AQ EM]
分类和应用:
文件页数/大小: 81 页 / 2574 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P258N  
8-Bit Microprocessor with OTP ROM  
Bit 3 (PSWE): Prescaler enable bit for WDT  
0 = prescaler disable bit, WDT rate is 1:1  
1 = prescaler enable bit, WDT rate is set as Bit2 ~ Bit0  
Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits  
PSW2 PSW1 PSW0 WDT Rate  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2  
1:4  
1:8  
1:16  
1:32  
1:64  
1:128  
1:256  
6.2.11 IOCF0 (Interrupt Mask Register)  
7
6
5
4
3
2
1
0
LPWTIE HPWTIE TCCCIE  
TCCBIE  
TCCAIE  
EXIE  
ICIE  
TCIE  
NOTE  
IOCF0 register is both readable and writable  
Individual interrupt is enabled by setting its associated control bit in the IOCF0 and in  
IOCE0 Bit 5 to "1".  
Global interrupt is enabled by the ENI instruction and is disabled by the DISI  
instruction. Refer to Fig. 6-7 (Interrupt Input Circuit) under Section 6.6 (Interrupt).  
Bit 7 (LPWTIE): LPWTIF interrupt enable bit  
0 = Disable LPWTIF interrupt  
1 = Enable LPWTIF interrupt  
Bit 6 (HPWTIE): HPWTIF interrupt enable bit  
0 = Disable HPWTIF interrupt  
1 = Enable HPWTIF interrupt  
Bit 5 (TCCCIE): TCCCIF interrupt enable bit  
0 = Disable TCCCIF interrupt  
1 = Enable TCCCIF interrupt  
Bit 4 (TCCBIE): TCCBIF interrupt enable bit  
0 = Disable TCCBIF interrupt  
1 = Enable TCCBIF interrupt  
Product Specification (V1.0) 06.16.2005  
21  
(This specification is subject to change without further notice)  
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