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EM78P259NSO14J 参数 Datasheet PDF下载

EM78P259NSO14J图片预览
型号: EM78P259NSO14J
PDF下载: 下载PDF文件 查看货源
内容描述: [EM78Q153SN EM78P153SP EM78P153SN EM78156EH EM78156EP EM78156EM EM78156EKM EM78Q156ELP EM78Q156ELM EM78Q156ELKM EM78P156ELP EM78P156ELM EM78P156ELKM EM78P156NP EM78P156NM EM78447SH EM78447SAP EM78447SAM EM78447SAS EM78447SBP EM78447SBWM EM78Q447SH EM78Q447SAP EM78Q447SAM EM78Q447SBP EM78Q447SBWM EM78P447SAP EM78P447SAM EM78P447SAS EM78P447SBP EM78P447SBWM EM78Q257 EM78Q257AP EM78Q257AM EM78Q257BP EM78Q257BM EM78P257AP EM78P257AM EM78P257BP EM78P257BM EM78451H EM78451P EM78451AQ EM]
分类和应用:
文件页数/大小: 81 页 / 2574 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P258N  
8-Bit Microprocessor with OTP ROM  
6.2.9 IOCD0 (Pull-high Control Register)  
7
6
5
4
3
2
1
0
/PH57  
/PH56  
/PH55  
/PH54  
/PH53  
/PH52  
/PH51  
/PH50  
NOTE  
IOCD0 register is both readable and writable  
Bit 7&Bit6:  
Not used, fixed to “1”.  
Bit 5 (/PH55): Control bit is used to enable the pull-high of the P55 pin.  
0 = Enable internal pull-high;  
1 = Disable internal pull-high.  
Bit 4 (/PH54): Control bit is used to enable the pull-high of the P54 pin.  
Bit 3 (/PH53): Control bit is used to enable the pull-high of the P53 pin.  
Bit 2 (/PH52): Control bit is used to enable the pull-high of the P52 pin.  
Bit 1 (/PH51): Control bit is used to enable the pull-high of the P51 pin.  
Bit 0 (/PH50): Control bit is used to enable the pull-high of the P50 pin.  
6.2.10 IOCE0 (WDT Control & Interrupt Mask Registers 2)  
7
6
5
4
3
2
1
0
WDTE  
EIS  
ADIE  
-
PSWE  
PSW2  
PSW1  
PSW0  
Bit 7 (WDTE): Control bit is used to enable Watchdog Timer  
0 = Disable WDT  
1 = Enable WDT  
WDTE is both readable and writable  
Bit 6 (EIS):  
Control bit is used to define the function of the P60 (/INT) pin  
0 = P60, bi-directional I/O pin  
1 = /INT, external interrupt pin. In this case, the I/O control bit of P60  
(Bit 0 of IOC60) must be set to "1"  
NOTE  
When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin  
can also be read by way of reading Port 6 (R6). Refer to Fig. 6-3 (I/O Port and I/O  
Control Register Circuit for P60(/INT)) under Section 6.4 (I/O Ports).  
EIS is both readable and writable.  
Bit 5 (ADIE): ADIF interrupt enable bit  
0 = disable ADIF interrupt  
1 = enable ADIF interrupt  
Bit 4:  
Not used, fixed to “0”.  
20 •  
Product Specification (V1.0) 06.16.2005  
(This specification is subject to change without further notice)  
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