EM78815
8-Bit Microcontroller
Bit 7 (CAS) : Call Waiting decoding output
0/1 → CW data valid / No data
7.2.20.4 Page 3 UART transmitter data buffer
Bit 7
URT7
R/W-X
Bit 6
URT6
R/W-X
Bit 5
URT5
R/W-X
Bit 4
URT4
R/W-X
Bit 3
URT3
R/W-X
Bit 2
URT2
R/W-X
Bit 1
URT1
R/W-X
Bit 0
URT0
R/W-X
Bit 0~Bit 7(URT0~URT7) : Low 8-bit UART transmitter data buffer
7.2.21 RF Interrupt flag
Bit 7
RBF/STD FSK/CW
R/W-0 R/W-0
Bit 6
Bit 5
Bit 4
UART
R/W-0
Bit 3
DED
Bit 2
CNT2
R/W-0
Bit 1
CNT1
R/W-0
Bit 0
TCC
−
×
R/W-0
R/W-0
Note: "1" means interrupt request
"0" means non-interrupt
Bit 0 (TCC) : TCC timer overflow interrupt flag
Set when TCC timer overflows.
Bit 1 (CNT1) : Counter 1 timer overflow interrupt flag
Set when Counter 1 timer overflows.
Bit 2 (CNT2) : Counter 2 timer overflow interrupt flag
Set when Counter 2 timer overflows.
Bit 3 (DED) : Differential Energy Detector (DED) Interrupt flag output data. If
DEDD (RE Page 2 Bit 7) has a falling edge signal (or falling & rising
edge signal, switch by IOCE Page 1 Bit 5), the CPU will set this bit.
Bit 4 (UART) : Universal Asynchronous Receiver Transmitter interrupt flag. When
the transmitter buffer is empty, receiver buffer full or receiver data
error, this bit will be set.
Bit 5:
Bit 6 (FSK/CW) : FSK data or Call waiting data interrupt flag.
If FSKDATA or CAS has a falling edge trigger signal, the CPU will set
Undefined register. These bits are unimplemented, not for use.
this bit.
Bit 7 ( RBF/STD) : SPI data transfer complete or DTMF receiver signal valid interrupt
If serial IO's RBF signal has a rising edge signal (RBF set to "1" when
data is transferred completely), the CPU will set this bit. Or when the
DTMF receiver’s STD signal has a rising edge signal (the DTMF
decodes a DTMF signal).
IOCF is the interrupt mask register. User can read and clear.
46 •
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
