EM78815
8-Bit Microcontroller
Trigger edge is shown in the following table:
Signal
TCC
Trigger
Time out
Remark
Counter 1
Counter 2
DED
Time out
8/16 bits select by CONT register
Time out
Signal detect
Receiver full, Transmitter
empty or error (if enabled)
UART
FSK
Falling edge
Rising edge
RBF/STD
EM78815 MCU will store ACC, R3 status and R5 Page automatically after an
interrupt is triggered. It will be restored after instruction “RETI”.
7.2.21.1 Page 1 External Data ROM
Bit 7
EXA8
R/W-0
Bit 6
EXA7
R/W-0
Bit 5
EXA6
R/W-0
Bit 4
EXA5
R/W-0
Bit 3
EXA4
R/W-0
Bit 2
EXA3
R/W-0
Bit 1
EXA2
R/W-0
Bit 0
EXA1
R/W-0
Bit 0~Bit 7(EXA1~EXA8) : Expanding Data ROM start address A1~A8
7.2.21.2 Page 2 External Data ROM
Bit 7
EXA16
R/W-0
Bit 6
EXA15
R/W-0
Bit 5
EXA14
R/W-0
Bit 4
EXA13
R/W-0
Bit 3
EXA12
R/W-0
Bit 2
EXA11
R/W-0
Bit 1
EXA10
R/W-0
Bit 0
EXA9
R/W-0
Bit 0~Bit 7(EXA9~EXA16) : Expanding Data ROM start address A9~A16,,IOCB
Page 1 Bit 7 is the MSB (EXA17) for Expanding Data ROM start address.
7.2.21.3 Page 3 Unused
7.2.22 R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers
7.3 Special Purpose Registers
7.3.1 A (Accumulator)
Internal data transfer, or instruction operand holding
It's not an addressable register.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
47
ELAN [ ELAN MICROELECTRONICS CORP ]
