EM78815
8-Bit Microcontroller
7.2.19 RD Port D I/O Data, Data RAM Address
7.2.19.1 Page 0 Port D I/O Data, Data RAM Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
R/W-X
Bit 0 ~ Bit 7 (PD0 ~ PD7) : 7-bit Port D ( 0~6 ) I/O data register
User can use the IOC register to define each bit either as input or output.
7.2.19.2 Page 1 Data RAM Address 1 (Low 8 bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RAM1A7 RAM1A6 RAM1A5 RAM1A4 RAM1A3 RAM1A2 RAM1A1 RAM1A0
R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X R/W-X
Bit 0~Bit 7 (RAM1A0 ~ RAM1A7) : Data RAM address1 (Address 0 to Address 7) for
RAM reading or writing
7.2.19.3 Page 2 Undefined Register
7.2.19.4 Page 3 Undefined Register
These two register are unimplemented, not for use.
7.2.20 RE Interrupt Flag 1, Data RAM Address 1 (H) CAS, Key Scan
7.2.20.1 Page 0 Interrupt Flag 1
Bit 7
INT7
Bit 6
INT6
Bit 5
INT5
Bit 4
INT4
Bit 3
INT3
Bit 2
INT2
Bit 1
INT1
Bit 0
INT0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Interrupt flag registers. User can only clear these bits from 1 to 0 but cannot
set them from 0 to 1.
Bit 0 (INT0) : External INT0 pin interrupt flag
If Port 70 has a falling edge trigger signal, the CPU will set this bit.
Bit 1 (INT1) : External INT1 pin interrupt flag
If Port 71 has a falling edge trigger signal, the CPU will set this bit.
Bit 2 (INT2) : External INT2 pin interrupt flag
If Port 72 has a falling edge trigger signal, the CPU will set this bit.
Bit 3 (INT3) : External INT3 pin interrupt flag
If Port 73 has a falling edge trigger signal, the CPU will set this bit.
Bit 4 (INT4) : External INT4 pin interrupt flag
If Port 74 has a falling edge trigger signal, the CPU will set this bit.
Bit 5 (INT5) : External INT5 pin interrupt flag
If Port 75 has a falling edge trigger signal, the CPU will set this bit.
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Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
