EM78815
8-Bit Microcontroller
7.3.2 CONT (Control Register)
Bit 7
INT/EDGE
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT
TS
DAEN
PAB
RSR2
RSR1
RSR0
Bit 0 ~ Bit 2 (PSR0 ~ PSR2) : TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
1:2
WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
1:4
1:16
1:8
1:32
1:16
1:32
1:64
1:128
1:64
1:128
1:256
Bit 3 (PAB) :
Bit 4 (DAEN) :
Bit 5 (TS) :
Prescaler assigned bit
0/1 → TCC/WDT
Current DA enable control
0/1 → disable/enable
TCC signal source
Instruction clock / 16.384kHz
Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL
and Main clock selection. See Fig.15.
Bit 6 (INT) :
INT enable flag
0 → interrupt masked by DISI or hardware interrupt
1 → interrupt enabled by ENI/RETI instructions
Bit 7(INT_EDGE) : interrupt edge type of P77
0 → P77 's interrupt source is a rising and falling edge signal.
1 → P77 's interrupt source is a falling edge signal.
The CONT register is readable (CONTR) and writable (CONTW). There is an 8-bit
counter available as prescaler for the TCC or WDT. The prescaler is available for the
TCC only or WDT only at the same time.
An 8-bit counter is available for TCC or WDT determined by the status of Bit 3 (PAB)
of the CONT register. See the prescaler ratio in the CONT register. Fig. 25 depicts
the circuit diagram of TCC/WDT. Both TCC and prescaler will be cleared by
instructions which write to TCC each time. The prescaler will be cleared by the
WDTC and SLEP instructions, when in WDT mode.
The prescaler will not be cleared by SLEP instructions, when in TCC mode.
48 •
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
