EM77950
BB Controller
8.2.12 Carrier-Sense
Carrier-sense protocols are protocols in which a node (station) listens to the common
channel before it starts transmitting. The node tries to identify other transmissions in
order to avoid collision that might block its own transmission. In a wider perspective, a
network that applies carrier-sense protocol utilizes the channel bandwidth more
efficiently. A more efficient network enables lower power consumption to each node,
shorter delay and higher probability of reaching destination to each packet.
The BB uses one complimentary technique in order to achieve very wide-ranging
carrier-sense abilities. It has an internal implementation of RFWaves Network
Carrier-Sense algorithm. This enables it to avoid collision with other RFWaves stations
on its network or from other networks in the area.
While the Carrier-Sense status bit in SSR (CS) tells the MCU when not to transmit, the
two interrupt CS and LINK_DIS gives the MCU a flag when to transmit. LINK_DIS will
be invoked whenever any transmission has ended, while CS interrupt will be invoked
only when an RFWaves transmission has ended. An application can use some of the
above mechanisms though not all of them – according to its needs.
8.2.12.1 RFWaves Carrier-Sense Algorithm
Assuming our bit rate is 1Mbps. According to the described bit structure (Section 8.2.5
Bit Structure), the time difference between two rising on DATA_IO must be an integer
number of 1μsec. If we take into account the frequency deviation between the two BB
oscillators, the time difference between two rising edges is 1μsec± . The depends
on the frequency deviation between the two BB oscillators. The BB uses this quality in
its carrier-sense algorithm. If an N (N = (CSR (0:3) * 2) + 2) number of “1” bit, where
each is preceded by at least one “0” bit, are received with time difference of an integer
number of 1μsec between two consecutive “1” bit, then the CS flag in SSR equals ‘1’.
Basically, the BB counts “0” to “1” transits on DATA_IO input, where the time difference
between two transits should be an integer number (≥ 2) of 1μsec. The number of
consecutive “1” bit that conforms to this rule is counted in the following example (Figure
8-2) in ONE_CNT counter. ONE_CNT is incremented only if a “1” bit that comes after a
“0” bit is received, where the time gap between the “1” bit and the preceding “1” bit is as
mentioned above. If the time difference between two consecutive “1” bit is out of the
allowed deviation, the ONE_CNT is reset. ONE_CNT is also reset if the number of
consecutive “0” exceeds (CSR (4:7) * 2) + 2, where CSR is the last “1” bit received is
counted in ZERO_CNT. ZERO_CNT is reset each time “1” bit is received.
Both M and N values are determined in CSR register (CSR (7:4) and CSR (3:0)
accordingly).
50 •
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
