EM77950
BB Controller
RX_FIFO Overflow Status Bit – bit RX_OF in SSR indicates when an overflow event
has occurred. If a received byte is written to a full RX_FIFO, the last byte in the
RX_FIFO is override and the RX_OF flag is raised.
The RX_AF interrupt should invoke the MCU to read from the RX_FIFO. Using the
almost full event gives the MCU 32μsec (4 bytes × 8 μsec) to respond before it loses
data, assuming a bit rate of 1Mbps. It uses most of the RX_FIFO size even if the
response latency of the MCU is very short.
Should the MCU not respond properly to the almost full event, and an input byte is
written to the RX_FIFO when it was full, then this byte would overrun the last byte in the
RX_FIFO, meaning the byte that immediately preceded it.
LOCK_OUT interrupt should also trigger the MCU to read from the RX_FIFO. In case
a packet has ended and the RX_AF interrupt was not invoked, the MCU should be
triggered by the LOCK_OUT interrupt.
8.2.8 TX FIFO
Transmitting data is done by writing it to the TX_FIFO.
The interface to the TX_FIFO is similar to all the other write-only registers in BB.
The purpose of the TX_FIFO is to reduce the real-time from the MCU in a transmitting
process. The TX_FIFO enables the MCU, theoretically, to write to the TX_FIFO every
128μsec and not every 8μsec, as is the case with a regular 8-bit shift register.
The TX_FIFO Status Register (TFSR) indicates the number of bytes in the TX_FIFO.
The TX_FIFO can also invoke an MCU interrupt if TX_FIFO almost empty event
occurs.
Almost empty flag will rise when there are only 4 empty bytes in the TX_FIFO.
It gives the MCU 32μsec to respond time to reload the TX_FIFO in case the transmitted
packet is bigger than the TX_FIFO.
In case the MCU writes to a full TX_FIFO, then this byte overruns the last byte in the
TX_FIFO, meaning the byte that was written just before it. Writing to a full TX_FIFO set
the TX_OF flag in SSR.
8.2.9 Interrupt Driver
The INT output pin is the summation of all interrupt sources in the BB. Whenever an
interrupt event has occurred and this interrupt is enabled (IER), INT will go from low to
high. INT will remain high until IIR register is read. The IIR register contains all the
interrupts event that have occurred since the last read. It shows the event only for
enabled interrupts. If an interrupt is disabled, even if the event that invoked this
interrupt has occurred, the interrupt flag will be low. The IER register is used to
enable/disable each of the interrupt. SCR4 (0) enables/disables all the interrupts.
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
