EM77950
BB Controller
Both the receiving node and the transmitting node in the network have to be in the
same CRC mode.
The BB can apply CRC in three different ways:
16-Bit CRC – using polynomial 1+X2+X15+X16.
8-Bit CRC – using polynomial 1+X+X2+X8.
No CRC.
This gives each application the flexibility to choose the adequate amount of overhead it
adds to each packet and the corresponding level of protection the CRC code has.
If CRC is enabled, then BB calculates the CRC of each incoming packet. It does not
put the received CRC value in the RX_FIFO. It just puts the result of its calculation in
the RX_FIFO as the last byte of the packet:
0x55 – CRC received correctly.
0xAA – CRC was received incorrectly.
The status bit SSR (0) stores the result of the last received packet.
8.2.7 RX FIFO
All received bytes are transferred to the RX_FIFO. The RX_FIFO stores the input data
until the MCU reads the data from it.
CRC and Preamble bytes are not transferred to the RX_FIFO.
The RX_FIFO is accessed just like all the other read-only registers in the BB. The MCU
cannot write to RX_FIFO - it can only read from it.
RX_FIFO_SIZE is 16 bytes.
The purpose of having an input FIFO in BB is to reduce the real-time burden from the
MCU. The FIFO is used as a buffer, which theoretically enables the MCU to read the
incoming data every RX_FIFO_SIZE × 8 bit/byte × 1μsec = 128 μsec, and not every
1μsec in the case of serial input, or every 8μsec in the case where there is a serial to
parallel converter.
The actual buffer size for practical use is a bit smaller, since the MCU response time is
taken into account.
The MCU has three ways to learn about the RX_FIFO status:
The RX FIFO Status Register (RFSR) contains the number of bytes in the RX_FIFO.
BB INT pin. I f configured appropriately, the INT pin will be “1” each time RX_FIFO is
almost full. This invokes an MCU interrupt if the INT pin is connected to the MCU
external interrupt pin.
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Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)