EM77950
BB Controller
The number of “0” bits that will cause a discharge in Mechanism 2 are determined by
bits ZERO_DISCH_CNT [0:2].
For both mechanisms, the discharge time is determined by CAP_DIS_PERIOD in
SCR3.
Discharge is done by setting RX_TX pin to ‘1’ for a certain time and then setting it back
to ‘0’.
(*) More detailed explanations of the reference capacitor discharge algorithms and
motivations are can be found in the “RFW - Capacitor Discharge.pdf” document.
8.2.14 Changing BB Configuration
It is not recommended to change the BB configuration while it is in the middle of
receiving or transmitting a packet.
Thus, before writing to any of the BB control registers (such as BLR, PRE-L, PRE-H,
PPR etc), do thefollowing:
1.
2.
3.
Change TX_RX mode to RX.
Disable Preamble search (SEARCH_EN in SCR2)
Stop all RX receiving – RX_STOP.
It is then safe to change the BB configuration.
8.2.15 Input Synchronizer
Handling asynchronous inputs to the BB.
Synchronized
Input
Asynchronous
SET
CLR
SET
CLR
Input
S
R
Q
Q
S
R
Q
Q
CLK
8.3 Register Description
The registers in the BB are divided into three groups:
•
•
•
Read-only registers. Mainly status registers.
Write-only registers. Mainly control registers.
Read and write registers.
In case of an RST pulse, all register are set to their default value.
52 •
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
