EM77950
BB Controller
The maximum bit rate is: 1Mbps.
The minimum bit rate is: 10Kbps (TBD)
However it is recommended to work only at 1Mbps since reducing the bit rate does not
change the energy of a transmitted bit. Meaning, reducing the bit-rate does not improve
the bit error rate or the range between the transmitter and the receiver.
Bit Length Register (BLR) determines the number of clock cycles per bit (bit period).
BLR value is given a fixed offset of 6, since the minimum number of clock cycles in one
bit is 6.
Bit Rate = Oscillator/(BLR+6).
The BB outputs (for the RFW-102) the bit structure shown below.
Bit "1" Structure - Odd
Clock Number
Bit "1" Structure - Even
Clock Number
Clock Period
Bit Period
Fig. 8-3 Bit Structure of the BB output to the RFW-102
Clock Period
Bit Period
In the odd number of clocks example BLR=1.
In the even number of clocks example BLR=2.
The number of clocks when the line is “1” is determined as follows:
⎡
⎢
⎤
BLR + 6
⎛
⎞
⎟
Number of "1"s = FLOOR
−1
⎥
⎜
2
⎝
⎢
⎣
⎠
⎥
⎦
In case of “0” bit, BB output “0” value for BLR+6 clock pulses.
* FLOOR – Rounds towards zero.
8.2.6 CRC
The BB adds additional CRC information to each packet in the transmitter module, in
order to enable the protocol to detect errors. The CRC is a redundant code, which is
calculated and added to each packet on the transmitter side. The CRC is also
calculated on the receiver side. The CRC calculation results of the receiver and the
CRC field in the received packet are compared in the receiver using the CRC module in
the chip. If CRC results are equal, then the receiver knows with reasonable probability
that the packet was received correctly. If the CRC results are not equal then the
receiver knows with probability 1 that the packet was received incorrectly.
The CRC mode is configured in the PPR (3:4) register.
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
