EM77950
BB Controller
8.2.4 Refresh Bit
When receiving a valid packet, The RFWaves modem (PHY layer) has to receive a “1”
symbol each time a certain period has elapsed in order to maintain its sensitivity. The
time between adjacent “1” symbols is determined by the value of the reference
capacitor. This constraint is transparent to the application layer since the BB adds a “1”
symbol (refresh bit) if too many “0” symbols are transmitted consecutively. On the
receiver side, these additional “1” symbols (refresh bits) are removed by the BB.
This feature is transparent to the application layer. The application layer has only to
initialize the maximum allowed number of consecutive x“00” bytes.
The BB has the flexibility to add a refresh bit every 1 to 7 bytes. This is configured by
RB (0:2) bits in PPR register. The value of RB (0:2) bits in PPR register determines the
overhead the refresh bit has on the throughput of the link.
The refresh bit does not add substantial overhead on the bit stream, since it is only
added when the number of consecutive x”00” bytes exceeds a certain value.
The data that is sent is application dependent, so the application can be adjusted in
order that there will be a negligible probability of this event happening.
Typical RFWaves capacitor: C=1nF.
Normal discharge current = 200nA.
Each 10mV on the capacitor represent 1dB in receiving power.
I
200nA
1dB
=
=
C ⋅V 1nF ⋅10mV 50μ sec
The capacitor is charged with each received “1” symbol.
The receiver is allowed to lose 1dB before a new “1” is to be received.
Thus, after each 50 consecutive “0” bits in 1Mbps (50μsec) a “1” symbol should be
sent.
In this case, setting RB [0:2] in PPR register to be 5 (“101”) would be sufficient
(5 bytes = 40bits).
When RB (0:2) bits are set to “000” a refresh bit is added to every transmitted byte,
regardless of its content. This introduces a constant overhead of 12.5%.
8.2.5 Bit Structure
The BB uses an oscillator ranging from 6~24 MHz. In order to determine the output and
input bit rate, the BB must be configured to the number of clocks consisting each bit.
This gives the applicator the control over the bit rate with certain restrictions. Each bit
must have at least 6 clock cycles.
44 •
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
