EM77950
BB Controller
8.1.4 BB Architecture
INT
Interrupt
Handler
Address
Filter
Serial
Input /
Output
Preamble
Correlation
RX FIFO
Receiver
Address
Bus
Control and
Status
CRC
Registers
Data Bus
TX FIFO
Transmitter
Fig. 8-2 BB Block Diagram
8.2 BB Description
8.2.1 Reset
A reset is achieved by holding the RST pin high for at least TBD oscillator cycles.
To ensure good power-up, a reset should be given to BB after power-up.
8.2.2 Power Saving Modes
The BB was designed to work in similar working modes as a typical MCU.
These modes enable the system to conserve power when the BB is not in use.
8.2.2.1 Power-Down Mode
The MCU is able to halt all activity in BB by stopping its clock. This enables the MCU to
reduce the power consumption of the BB to a minimum.
All registers and FIFOs retain their values when BB is in power-down mode.
BB enters power-down mode by setting bit TBD in register TBD to “1”. This bit is set by
the MCU and cleared by BB.
BB goes back to working mode by setting CS_n input pin to “0” for TBD msec.
The wake-up time of BB from power-down mode to fully operating mode is TBD msec.
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Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
