EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
As soon as Chip Select (S#) is driven High, the self-timed Page Program cycle (whose
duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register
may be read to check the value of the (BUSY) bit. The (BUSY) bit is “1” during the self-timed
Page Program cycle, and is “0” when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page that is protected by the Block Protect (BP1,
BP0) bits (see Tables 2 and 4) will not be executed.
Block Erase
The Block Erase (BE) instruction sets all bits inside the chosen block to “1” (FFh). Before it
can be accepted, a Write Enable (WREN) instruction must be previously executed. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch
(WEL). The Block Erase (BE) instruction is entered by driving the Chip Select (S#) Low,
followed by the instruction code, and three address bytes on Serial Data Input (D). Any
address inside the Block (see Table 3) is a valid address for the Block Erase (BE) instruction.
Chip Select (S#) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 17. Chip Select (S#) must be driven High after
the eighth bit of the last address byte has been latched in, otherwise, the Block Erase (BE)
instruction will not execute. As soon as the Chip Select (S#) is driven High, the self-timed
Block Erase cycle (whose duration is tSE) is initiated. While the Block Erase cycle is in
progress, the Status Register may be read to check the value of the (BUSY) bit. The (BUSY)
bit is “1” during the self-timed Block Erase cycle, and is “0” when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a page that is protected by the Block Protect (BP1,
BP0) bits (see Tables 3 and 2) will not be executed.
Chip Erase
The Chip Erase (CE) instruction sets all bits of the memory array to “1” (FFh). Before it can
be accepted, a Write Enable (WREN) instruction must be previously executed. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch
(WEL). The Chip Erase (CE) instruction is entered by driving the Chip Select (S#) Low,
followed by the instruction code on Serial Data Input (D). The Chip Select (S#) must be
driven Low for the entire duration of the sequence.
This specification is subject to change without further notice. (11.08.2004 V1.0)
Page 15 of 30
ELAN [ ELAN MICROELECTRONICS CORP ]
