EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 10) sets the Write Enable Latch (WEL) bit to “1”.
The Write Enable Latch (WEL) bit must be set prior to the Page Program (PP), Block Erase
(BE), Chip Erase (CE), and Write Status Register (WRSR) instructions. The Write Enable
(WREN) instruction is entered by driving Chip Select (S#) Low, sending the instruction code,
and then driving Chip Select (S#) High.
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 11) resets the Write Enable Latch (WEL) bit to
“0.” The Write Disable (WRDI) instruction is entered by driving Chip Select (S#) Low,
sending the instruction code, and then driving the Chip Select (S#) High. The Write Enable
Latch (WEL) bit is reset under the following conditions:
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Power-up
Write Disable (WRDI) instruction completed
Write Status Register (WRSR) instruction completed
Page Program (PP) instruction completed
Block Erase (BE) instruction completed
Chip Erase (CE) instruction completed
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the 8-bit Status Register to be read.
The Status Register may be read any time, even while a Program, Erase, or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the (BUSY) bit before sending a new instruction to the device. It is also allowed to read
the Status Register continuously, as shown in Figure 12.
An improvement in the time to Write Status Register (WRSR), Program (PP), or Erase (SE,
BE or CE) can be achieved by not waiting for the worst-case delay (tW, tPP, tSE, tBE or tCE).
The (BUSY) bit is provided in the Status Register so that the system application program can
monitor its value, polling it to “0” when the previous Write cycle, Program cycle, or Erase cycle
is completed.
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it is accepted, a Write Enable (WREN) instruction must be executed first.
After the Write Enable (WREN) instruction has been decoded and executed, the device sets
the Write Enable Latch (WEL).
This specification is subject to change without further notice. (11.08.2004 V1.0)
Page 12 of 30
ELAN [ ELAN MICROELECTRONICS CORP ]
