EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
Instructions
All instructions, addresses, and data are shifted in and out of the device with the most
significant bit shifted first.
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S#) is driven Low. Then, the one-byte instruction code must be shifted in to the device with
the most significant bit entered first on Serial Data Input (D), and each bit being latched on the
rising edges of Serial Clock (C). The instruction set is listed in Table 7 below.
Depending on the instruction, the one-byte instruction code is followed by address bytes or
data bytes, or both, or none at all. Chip Select (S#) must be driven High after the last bit of
the instruction sequence has been shifted in.
At the end of a Page Program (PP), Block Erase (BE), Chip Erase (CE), or Write Status
Register (WRSR) instruction, Chip Select (S#) must be driven High exactly at a byte boundary.
Otherwise the instruction will be rejected and not executed. That is, Chip Select (S#) must be
driven High when the number of clock pulses after Chip Select (S#) being driven Low, is an
exact multiple of eight. All attempts to access the memory array during a Write Status
Register cycle, Program cycle, or Erase cycle are ignored, and the internal Write Status
Register cycle, Program cycle, or Erase cycle will continue ineffectively.
Address Dummy Data
Instruction
Description
One-byte Instruction Code
Bytes Bytes Bytes
WREN
WRDI
RDSR
WRSR
READ
FAST READ
PP
Write Enable
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 1000
1100 0111
1011 1001
0
0
0
0
3
3
3
3
0
0
0
0
0
0
0
1
0
0
0
0
0
Write Disable
0
Read Status Register
Write Status Register
Read Data Bytes
Read Data Bytes at Higher Speed
Page Program
1 to ∞
1
1 to ∞
1 to ∞
1 to 256
BE
Block Erase
0
0
0
CE
Chip Erase
DP
Deep Power-down
Release from Deep Power-down, and
Read Device ID
0
3
1 to ∞
RES
1010 1011
1001 0000
Release from Deep Power-down
Read Manufacturer/Device ID
0
0
0
3
0
RDID
1 to ∞
Table 7: Instruction Set
This specification is subject to change without further notice. (11.08.2004 V1.0)
Page 11 of 30
ELAN [ ELAN MICROELECTRONICS CORP ]
