HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Relationship Between Frequency and Minimum Latency
HM5225165B/
HM5225805B/
HM5225405B
Parameter
-75
-A6/B6
Frequency (MHz)
133
100
PC/100
Symbol
tCK (ns)
Symbol
7.5
10
Notes
Active command to column command
(same bank)
lRCD
3
2
1
Active command to active command
(same bank)
lRC
9
6
3
2
2
7
5
2
2
2
= [lRAS+ lRP]
1
Active command to precharge command
(same bank)
lRAS
lRP
lDPL
lRRD
1
1
1
1
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Tdpl
Active command to active command
(different bank)
Self refresh exit time
lSREX
lAPW
Tsrx
Tdal
1
5
1
4
2
Last data in to active command
(Auto precharge, same bank)
= [lDPL + lRP]
Self refresh exit to command input
lSEC
9
7
= [lRC]
3
Precharge command to high impedance
(CAS latency = 2)
lHZP
lHZP
lAPR
Troh
Troh
2
3
1
2
3
1
(CAS latency = 3)
Last data out to active command
(Auto precharge, same bank)
Last data out to precharge (early precharge)
(CAS latency = 2)
lEP
–1
–2
1
–1
–2
1
(CAS latency = 3)
lEP
Column command to column command
Write command to data in latency
DQM to data in
lCCD
lWCD
lDID
lDOD
lCLE
lRSA
Tccd
Tdwd
Tdqm
Tdqz
Tcke
Tmrd
0
0
0
0
DQM to data out
2
2
CKE to CLK disable
1
1
Register set to active command
1
1
Data Sheet E0082H10
52
ELPIDA [ ELPIDA MEMORY ]
