HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
CKE
V
IH
CS
RAS
CAS
WE
BS
code
C: b’
Address
valid
C: b
R: b
DQM,
DQMU/DQML
b+3
b’+1 b’+2 b’+3
b’
DQ (output)
b
High-Z
DQ (input)
l
RSA
l
l
RCD
RP
Output mask
l
= 3
RCD
Precharge
If needed
Mode
register
Set
Bank 3
Active
Bank 3
Read
CAS latency = 3
Burst length = 4
= V or V
IH
IL
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
CLK
CKE
V
IH
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
CS
RAS
= V or V
IH
IL
CAS
WE
BS
Address
DQM,
DQMU/DQML
R:a
C:a
R:b
C:b
C:b'
C:b"
DQ (output)
DQ (input)
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
Read
Precharge
V
IH
CKE
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
CS
RAS
= V or V
IH
IL
CAS
WE
BS
Address
DQM,
DQMU/DQML
R:a
C:a
a
R:b
C:b
C:b'
C:b"
High-Z
DQ (output)
DQ (input)
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b" b"+1b"+2 b"+3
Bank 0
Active
Bank 0
Write
Bank 3
Active
Bank 3
Write
Bank 0
Precharge
Bank 3
Write
Bank 3
Write
Bank 3
Precharge
Data Sheet E0082H10
56
ELPIDA [ ELPIDA MEMORY ]
