HM5164805F Series, HM5165805F Series
Self Refresh Mode (L-version)
HM5164805FL/HM5165805FL
-5
-6
Parameter
Symbol
tRASS
Min
100
90
Max
—
Min
100
110
–50
Max
—
Unit
µs
Notes
25
RAS pulse width (self refresh)
RAS precharge time (self refresh)
CAS hold time (self refresh)
tRPS
—
—
ns
25
tCHS
–50
—
—
ns
Notes: 1. AC measurements assume tT = 2 ns.
2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).
3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only; if tRCD is greater than the specified tRCD (max) limit, than the access time is
controlled exclusively by tCAC
.
4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH (min) and VIL (max).
8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max).
11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
13. tOFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included inthedata
sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the
data out pin will remain open circuit(high impedance) throughout the entire cycle; iftRWD ≥t RWD (min),
tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min),ortCWD ≥ tCWD (min),tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min),the
cycle is a read-modify-write and the data output will contain data read from the selected cell; if
neither of the above sets of conditions is satisfied, the condition of the data out (at access time)is
indeterminate.
15. tDS and tDH are referredto CAS leading edge in earlywrite cycles and to WE leading edgeindelayed
write or read-modify-write cycles.
16. tRASP defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA
.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data
to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes large
VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
Data Sheet E0098H10
15
ELPIDA [ ELPIDA MEMORY ]
