HM5164805F Series, HM5165805F Series
20. tHPC (min) can be achieved during a series of EDO page mode write cycles or EDO pagemoderead
cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page
mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the
specified tHPC (min) value. The value of CAS cycle time of mixed EDO page mode isshowninEDO
page mode mix cycle (1) and (2).
21. Data output turns off and becomes high impedance from later rising edge ofRAS and CAS. Hold
time and turn off time are specified by the timing specifications of laterrising edge of RAS andCAS
between tOHR and tOH and between tOFR and tOFF
.
22. tDOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing
reference level.
23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64ms
period on the condition a and b below.
a. Enter self refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within
15.6µs after exiting from self refresh mode.
24. In case of entering from RAS-only-refresh, it is necessary to executeCBRrefresh beforeand after
self refresh mode according as note 23.
25 At tRASS > 100 µs, self refresh mode is activated, and not activated at tRASS < 10 µs. It is undefined
within the range of 10 µs ≤ tRASS ≤ 100 µs. For tRASS ≥ 10 µs, it is necessary to satisfy tRPS
.
26. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timingwaveforms,their pins must be
applied VIH or VIL.
Data Sheet E0098H10
16
ELPIDA [ ELPIDA MEMORY ]
