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EDJ1108BABG-AC-E 参数 Datasheet PDF下载

EDJ1108BABG-AC-E图片预览
型号: EDJ1108BABG-AC-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 148 页 / 1878 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第51页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第52页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第53页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第54页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第56页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第57页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第58页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第59页  
EDJ1108BABG, EDJ1116BABG  
-AC, -AE, -AG  
1066  
-8A, -8C  
800  
Data rate (Mbps)  
Parameter  
Symbol  
min.  
max.  
min.  
max.  
Unit  
ps  
Notes  
DQS, /DQS rising edge output access  
time from rising CK, /CK  
DQS latching rising transitions to  
associated clock edges  
DQS falling edge hold time from rising  
CK  
DQS falling edge setup time to rising  
CK  
12, 13,  
37  
tDQSCK  
300  
0.25  
0.2  
+300  
400  
+400  
tDQSS  
tDSH  
tDSS  
0.25  
0.25  
0.2  
0.25  
tCK (avg) 24  
tCK (avg) 24, 36  
tCK (avg) 24, 36  
0.2  
0.2  
DQS input high pulse width  
DQS input low pulse width  
tDQSH  
tDQSL  
0.45  
0.45  
0.55  
0.55  
0.45  
0.45  
0.55  
0.55  
tCK (avg) 34, 35  
tCK (avg) 33, 35  
12, 13,  
tCK (avg)  
38  
12, 13,  
tCK (avg)  
38  
DQS output high time  
DQS output low time  
tQSH  
tQSL  
0.38  
0.38  
0.38  
4
0.38  
4
Mode register set command cycle time tMRD  
nCK  
Mode register set command update  
tMOD  
15  
15  
12  
0.9  
ns  
27  
27  
1, 19,  
38  
11, 12,  
13, 38  
delay  
tMOD  
12  
nCK  
Read preamble  
Read postamble  
tRPRE  
tRPST  
0.9  
tCK (avg)  
0.3  
0.3  
tCK (avg)  
Write preamble  
tWPRE  
tWPST  
tWR  
0.9  
0.3  
15  
0.9  
0.3  
15  
tCK (avg)  
tCK (avg)  
ns  
1
Write postamble  
Write recovery time  
1
26  
Auto precharge write recovery +  
precharge time  
Multi-Purpose register recovery time  
Read to write command delay  
(BC4MRS, BC4OTF)  
WR + RU  
WR + RU  
tDAL  
nCK  
nCK  
(tRP/tCK (avg))  
(tRP/tCK (avg))  
tMPRR  
tRTW  
1
1
29  
RL + tCCD/2 +  
2nCK WL  
RL + tCCD/2 +  
2nCK WL  
RL + tCCD +  
2nCK WL  
RL + tCCD +  
2nCK WL  
(BL8MRS, BL8OTF)  
tRTW  
18, 26,  
27  
18, 26,  
27  
Internal write to read command delay tWTR  
tWTR  
7.5  
7.5  
ns  
4
4
nCK  
Internal read to precharge command  
tRTP  
7.5  
7.5  
ns  
26, 27  
26, 27  
28  
delay  
tRTP  
4
4
nCK  
Active to READ with auto precharge  
command delay  
tRAP  
tRCD min  
tRCD min  
Minimum CKE low width for self-  
refresh entry to exit timing  
tCKE (min.)  
+1nCK  
tCKE (min.)  
+1nCK  
tCKESR  
Valid clock requirement after self-  
tCKSRE  
tCKSRE  
tCKSRX  
tCKSRX  
tXS  
10  
5
10  
5
ns  
27  
27  
27  
27  
27  
27  
refresh entry or power-down entry  
nCK  
ns  
Valid clock requirement before self-  
refresh exit or power-down exit  
10  
10  
5
5
nCK  
ns  
Exit self-refresh to commands not  
requiring a locked DLL  
tRFC (min.) +  
10  
5
tRFC (min.) +  
10  
5
tXS  
nCK  
Data Sheet E1248E40 (Ver. 4.0)  
55  
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