EDJ1108BABG, EDJ1116BABG
Notes for AC Electrical Characteristics
Notes: 1. Actual value dependent upon measurement level definitions that are TBD.
2. Commands requiring locked DLL are: READ (and READA) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register.
5. Value must be rounded-up to next integer value.
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. ODT turn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn on.
ODT turn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon.
8. ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.) is
when the bus is in high impedance. Both are measured from ODTLoff.
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer.
10. WR in clock cycles as programmed in MR0.
11. The maximum read postamble is bound by tDQSCK(min.) plus tQSH(min.) on the left side and
tHZ(DQS)(max.) on the right side.
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input
clock jitter, this parameter needs to be derated by TBD.
13. Value is only valid for RON34.
14. Single ended signal parameter. Refer to the section of tLZ (DQS), tLZ (DQ), tHZ (DQS), tHZ (DQ) Notes
for definition and measurement method.
15. tREFI depends on operating case temperature (TC).
16. tIS(base) and tIH(base) values are for 1V/ns command/address single-ended slew rate and 2V/ns CK,
/CK differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins
except /RESET, VREF(DC) = VREFCA(DC). See Address / Command Setup, Hold and Derating section
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, /DQS
differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except
/RESET, VREF(DC) = VREFCA(DC). See Data Setup, Hold and Slew Rate Derating section.
18. Start of internal write transaction is definited as follows:
For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.
For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
19. The maximum read preamble is bound by tLZ(DQS)(min.) on the left side and tDQSCK(max.) on the right
side.
20. CKE is allowed to be registered low while operations such as row activation, precharge, auto precharge or
refresh are in progress, but power-down IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered low after a refresh command once tREFPDEN(min.) is satisfied,
there are cases where additional time such as tXPDLL(min.) is also required. See Figure Power-Down
Entry/Exit Clarifications - Case 2.
22. tJIT(duty) = ± { 0.07 × tCK(avg) – [(0.5 - (min (tCH(avg), tCL(avg))) × tCK(avg)] }.
For example, if tCH/tCL was 0.48/0.52, tJIT(duty) would calculate out to ±125ps for DDR3-800.
The tCH(avg) and tCL(avg) values listed must not be exceeded.
23. These parameters are measured from a command/address signal (CKE, /CS, /RAS, /CAS, /WE, ODT,
BA0, A0, A1, etc.) transition edge to its respective clock signal (CK, /CK) crossing. The spec values are
not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are
relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24 These parameters are measured from a data strobe signal ((L/U/T)DQS, /DQS) crossing to its respective
clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters
should be met whether clock jitter is present or not.
25. These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge
to its respective data strobe signal ((L/U/T)DQS/DQS) crossing.
Data Sheet E1248E40 (Ver. 4.0)
58
ELPIDA [ ELPIDA MEMORY ]
