EDJ1108BABG, EDJ1116BABG
-GL, -GN
1600
-DG, -DJ
1333
Data rate (Mbps)
Parameter
Symbol
min.
max.
min.
0.38
max.
Unit
Notes
12, 13,
38
DQ output hold time from DQS, /DQS tQH
DQS, /DQS rising edge output access
time from rising CK, /CK
DQS latching rising transitions to
associated clock edges
DQS falling edge hold time from rising
CK
DQS falling edge setup time to rising
CK
0.38
−225
−0.27
0.18
0.18
tCK (avg)
12, 13,
37
tDQSCK
225
−255
−0.25
0.2
255
ps
tDQSS
tDSH
tDSS
0.27
0.25
tCK (avg) 24
tCK (avg) 24, 36
tCK (avg) 24, 36
0.2
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK (avg) 34, 35
tCK (avg) 33, 35
12, 13,
tCK (avg)
38
12, 13,
tCK (avg)
38
DQS output high time
DQS output low time
tQSH
tQSL
0.40
0.40
0.40
4
0.40
4
Mode register set command cycle time tMRD
nCK
Mode register set command update
tMOD
15
15
12
0.9
ns
27
27
1, 19,
38
11, 12,
13, 38
delay
tMOD
12
nCK
Read preamble
Read postamble
tRPRE
tRPST
0.9
tCK (avg)
0.3
0.3
tCK (avg)
Write preamble
tWPRE
tWPST
tWR
0.9
0.3
15
0.9
0.3
15
tCK (avg) 1
Write postamble
tCK (avg) 1
Write recovery time
ns
26
Auto precharge write recovery +
precharge time
Multi-Purpose register recovery time
Read to write command delay
(BC4MRS, BC4OTF)
WR + RU
WR + RU
tDAL
nCK
nCK
(tRP/tCK (avg))
(tRP/tCK (avg))
tMPRR
tRTW
1
1
29
RL + tCCD/2 +
2nCK − WL
RL + tCCD/2 +
2nCK − WL
RL + tCCD +
2nCK − WL
RL + tCCD +
2nCK − WL
(BL8MRS, BL8OTF)
tRTW
18, 26,
27
18, 26,
27
Internal write to read command delay tWTR
tWTR
7.5
7.5
ns
4
4
nCK
Internal read to precharge command
tRTP
7.5
7.5
ns
26, 27
26, 27
28
delay
tRTP
4
4
nCK
Active to READ with auto precharge
command delay
tRAP
tRCD min
tRCD min
Minimum CKE low width for self-refresh
entry to exit timing
tCKE (min.)
+1nCK
tCKE (min.)
+1nCK
tCKESR
Valid clock requirement after self-
refresh entry or power-down entry
tCKSRE
tCKSRE
10
5
10
5
ns
27
27
nCK
Data Sheet E1248E40 (Ver. 4.0)
51
ELPIDA [ ELPIDA MEMORY ]
