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EDJ1108BABG-AC-E 参数 Datasheet PDF下载

EDJ1108BABG-AC-E图片预览
型号: EDJ1108BABG-AC-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 148 页 / 1878 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第50页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第51页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第52页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第53页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第55页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第56页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第57页浏览型号EDJ1108BABG-AC-E的Datasheet PDF文件第58页  
EDJ1108BABG, EDJ1116BABG  
AC Characteristics [DDR3-1066, 800]  
-AC, -AE, -AG  
1066  
-8A, -8C  
800  
Data rate (Mbps)  
Parameter  
Symbol  
min.  
max.  
3333  
min.  
max.  
3333  
Unit  
ps  
Notes  
6
Clock cycle time Average CL = X  
Minimum clock cycle time  
(DLL-off mode)  
tCK(avg)  
1875  
2500  
tCK(DLL-off)  
8
8
ns  
Average duty cycle high-level  
tCH (avg)  
tCL (avg)  
0.47  
0.47  
0.53  
0.53  
0.47  
0.47  
0.53  
0.53  
tCK (avg)  
tCK (avg)  
Average duty cycle low-level  
11.25 (AC)  
13.1 (AE)  
15 (AG)  
11.25 (AC)  
13.1 (AE)  
15 (AG)  
48.75 (AC)  
50.6 (AE)  
52.5 (AG)  
12.5 (8A)  
15 (8C)  
Active to read or write command delay tRCD  
ns  
ns  
ns  
26  
26  
26  
12.5 (8A)  
15 (8C)  
Precharge command period  
tRP  
tRC  
Active to active/auto-refresh command  
time  
50 (8A)  
52.5 (8C)  
Active to precharge command  
Active bank A to active bank B  
command period  
tRAS  
37.5  
7.5  
4
9 × tREFI 37.5  
9 × tREFI ns  
26  
tRRD  
tRRD  
10  
4
ns  
26, 27  
26, 27  
26, 27  
26, 27  
26  
(x8)  
nCK  
Active bank A to active bank B  
command period  
(x16)  
Four active window  
(x8)  
(x16)  
tRRD  
tRRD  
10  
10  
4
ns  
4
nCK  
ns  
tFAW  
tFAW  
tIH (base)  
37.5  
50  
40  
50  
275  
ns  
26  
Address and control input hold time  
(VIH/VIL (DC) levels)  
200  
ps  
16, 23  
Address and control input setup time  
(VIH/VIL (AC) levels)  
Address and control input setup time tIS (base)  
(VIH/VIL (AC150) levels)  
DQ and DM input hold time  
(VIH/VIL (DC) levels)  
DQ and DM input setup time  
(VIH/VIL (AC) levels)  
Control and Address input pulse width  
for each input  
DQ and DM input pulse width for each  
input  
tIS (base)  
125  
200  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
16, 23  
16, 23,  
31  
125 + 150  
100  
200 + 150  
AC150  
tDH (base)  
150  
75  
17, 25  
17, 25  
32  
tDS (base)  
tIPW  
25  
780  
900  
600  
tDIPW  
490  
32  
12, 13,  
14, 37  
12, 13,  
14, 37  
12, 13,  
14, 37  
12, 13,  
14, 37  
DQ high-impedance time  
tHZ (DQ)  
tLZ (DQ)  
tHZ (DQS)  
tLZ (DQS)  
300  
300  
300  
300  
150  
400  
400  
400  
400  
200  
DQ low-impedance time  
600  
600  
800  
800  
DQS, /DQS high-impedance time  
(RL + BL/2 reference)  
DQS, /DQS low-impedance time  
(RL 1 reference)  
DQS, /DQS -DQ skew, per group, per  
access  
/CAS to /CAS command delay  
tDQSQ  
tCCD  
ps  
12, 13  
4
4
nCK  
12, 13,  
38  
DQ output hold time from DQS, /DQS tQH  
Data Sheet E1248E40 (Ver. 4.0)  
0.38  
0.38  
tCK (avg)  
54  
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