EDJ1108BABG, EDJ1116BABG
Self-Refresh
The self-refresh command can be used to retain data in the DDR3 SDRAM, even if the rest of the system is powered
down. When in the self-refresh mode, the DDR3 SDRAM retains data without external clocking. The DDR3 SDRAM
device has a built-in timer to accommodate self-refresh operation. The Self-Refresh Entry (SELF) command is
defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock.
Before issuing the self-refresh entry command, the DDR3 SDRAM must be idle with all bank precharge state with
tRP satisfied. Also, on-die termination must be turned off before issuing Self-refresh entry command, by either
registering ODT pin low “ODTL + 0.5tCK” prior to the self-refresh entry command or using MRS to MR1 command.
Once the self-refresh entry command is registered, CKE must be held low to keep the device in self-refresh mode.
The DLL is automatically disabled upon entering Self-refresh and is automatically enabled (including a DLL-Reset)
upon exiting self-refresh.
When the DDR3 SDRAM has entered self-refresh mode all of the external control signals, except CKE and /RESET,
are “don’t care”. For proper self-refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ,
VREFCA and VREFDQ) must be at valid levels. The DRAM initiates a minimum of one refresh command internally
within tCKESR period once it enters self-refresh mode.
The clock is internally disabled during self-refresh operation to save power. The minimum time that the DDR3
SDRAM must remain in self-refresh mode is tCKESR. The user may change the external clock frequency or halt the
external clock tCKSRE clock cycles after self-refresh entry is registered, however, the clock must be restarted and
stable tCKSRX clock cycles before the device can exit self-refresh operation. To protect DRAM internal delay on
CKE line to block the input signals, one NOP (or DESL) command is needed after self-refresh entry.
The procedure for exiting self-refresh requires a sequence of events. First, the clock must be stable tCKSRX prior to
CKE going back high. Once a Self-Refresh Exit command (SREX, combination of CKE going high and either NOP
or DESL on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not
requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command
which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function
requirements (TBD) must be satisfied.
CKE must remain high for the entire self-refresh exit period tXSDLL for proper operation except for self-refresh
reentry. Upon exit from self-refresh, the DDR3 SDRAM can be put back into Self-refresh mode after waiting at least
tXS period and issuing one refresh command (refresh period of tRFC). NOP or DESL commands must be registered
on each positive clock edge during the self-refresh exit interval tXS. ODT must be turned off during tXSDLL.
The use of Self-refresh mode introduces the possibility that an internally timed refresh event can be missed when
CKE is raised for exit from self-refresh mode. Upon exit from self-refresh, the DDR3 SDRAM requires a minimum of
one extra refresh command before it is put back into self-refresh mode.
Ta
Tb
Tc Tc+1Tc+2
Td
Te
Tf Tf+1 Tf+2
Tg Tg+1
Th Th+1
CK, /CK
tCKSRE
tCKSRX
tXSDLL
tRP
tXS
4
2
2
3
3
*
*
*
* *
Valid Valid
1
*
Command
Valid Valid
PALL
SELF NOP
SREX
tCKESR
CKE
ODT
ODTLoff + 0.5 x tCK
Notes: 1. Only NOP or DESL commands.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
4. One NOP or DESL commands.
Self-Refresh Entry and Exit Timing
Data Sheet E1248E40 (Ver. 4.0)
121
ELPIDA [ ELPIDA MEMORY ]
