欢迎访问ic37.com |
会员登录 免费注册
发布采购

EDJ1116BBSE-8A-F 参数 Datasheet PDF下载

EDJ1116BBSE-8A-F图片预览
型号: EDJ1116BBSE-8A-F
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR3 SDRAM [1G bits DDR3 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 151 页 / 1895 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第53页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第54页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第55页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第56页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第58页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第59页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第60页浏览型号EDJ1116BBSE-8A-F的Datasheet PDF文件第61页  
EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE  
AC Characteristics [DDR3-1066, 800]  
-AE, -AG  
1066  
-8A, -8C  
800  
Data rate (Mbps)  
Parameter  
Symbol  
min.  
max.  
3333  
min.  
max.  
3333  
Unit  
ps  
Notes  
6
Clock cycle time Average CL = X  
Minimum clock cycle time  
(DLL-off mode)  
tCK(avg)  
tCK  
(DLL-off)  
1875  
2500  
8
8
ns  
Average duty cycle high-level  
tCH (avg)  
0.47  
0.47  
0.53  
0.53  
0.47  
0.47  
0.53  
0.53  
tCK (avg)  
tCK (avg)  
Average duty cycle low-level  
tCL (avg)  
Active to read or write  
command delay  
13.1 (AE)  
12.5 (8A)  
tRCD  
tRP  
ns  
ns  
ns  
ns  
26  
26  
26  
26  
15 (AG)  
15 (8C)  
13.1 (AE)  
15 (AG)  
50.6 (AE)  
52.5 (AG)  
12.5 (8A)  
15 (8C)  
50 (8A)  
52.5 (8C)  
Precharge command period  
Active to active/auto-refresh  
command time  
tRC  
9 ×  
tREFI  
9 ×  
tREFI  
Active to precharge command  
tRAS  
37.5  
37.5  
Active bank A to active bank B  
command period  
(x4/x8)  
Active bank A to active bank B  
command period  
(x16)  
Four active window  
(x4/x8)  
(x16)  
Address and control input hold time  
(VIH/VIL (DC) levels)  
tRRD  
7.5  
4
10  
4
ns  
26, 27  
26, 27  
26, 27  
26, 27  
26  
tRRD  
nCK  
ns  
tRRD  
10  
4
10  
4
tRRD  
nCK  
ns  
tFAW  
37.5  
50  
200  
40  
50  
275  
tFAW  
ns  
26  
tIH (base)  
ps  
16, 23  
Address and control input  
setup time  
tIS (base)  
125  
200  
ps  
ps  
16, 23  
(VIH/VIL (AC) levels)  
Address and control input  
tIS (base)  
AC150  
16, 23,  
31  
setup time  
125 + 150  
200 + 150  
(VIH/VIL (AC150) levels)  
DQ and DM input hold time  
tDH (base) 100  
tDS (base) 25  
150  
75  
ps  
ps  
17, 25  
17, 25  
(VIH/VIL (DC) levels)  
DQ and DM input setup time  
(VIH/VIL (AC) levels)  
Control and Address input pulse  
width  
tIPW  
780  
490  
900  
600  
ps  
32  
32  
for each input  
DQ and DM input pulse width for  
each input  
tDIPW  
ps  
ps  
ps  
ps  
ps  
12, 13,  
14, 37  
12, 13,  
14, 37  
12, 13,  
14, 37  
12, 13,  
14, 37  
DQ high-impedance time  
DQ low-impedance time  
tHZ (DQ)  
tLZ (DQ)  
tHZ (DQS)  
tLZ (DQS)  
300  
300  
300  
300  
150  
400  
400  
400  
400  
200  
600  
600  
800  
800  
DQS, /DQS high-impedance time  
(RL + BL/2 reference)  
DQS, /DQS low-impedance time  
(RL 1 reference)  
DQS, /DQS -DQ skew, per group,  
per access  
/CAS to /CAS command delay  
DQ output hold time from  
DQS, /DQS  
tDQSQ  
tCCD  
tQH  
ps  
12, 13  
4
4
nCK  
12, 13,  
38  
0.38  
0.38  
tCK (avg)  
Data Sheet E1375E50 (Ver. 5.0)  
57  
 复制成功!