EDJ1104BBSE, EDJ1108BBSE, EDJ1116BBSE
-AE, -AG
1066
-8A, -8C
800
Data rate (Mbps)
Parameter
Symbol
min.
max.
min.
max.
Unit
ps
Notes
DQS, /DQS rising edge output
access time from rising CK, /CK
DQS latching rising transitions to
associated clock edges
DQS falling edge hold time from
rising CK
DQS falling edge setup time to
rising CK
12, 13,
37
tDQSCK
−300
−0.25
0.2
+300
−400
−0.25
0.2
+400
tDQSS
tDSH
tDSS
0.25
0.25
tCK (avg) 24
tCK (avg) 24, 36
tCK (avg) 24, 36
0.2
0.2
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK (avg) 34, 35
tCK (avg) 33, 35
12, 13,
tCK (avg)
38
12, 13,
tCK (avg)
38
DQS output high time
tQSH
tQSL
tMRD
0.38
0.38
4
0.38
0.38
4
DQS output low time
Mode register set command
cycle time
nCK
Mode register set command
tMOD
tMOD
tRPRE
15
12
0.9
15
12
0.9
ns
27
27
1, 19,
38
11, 12,
13, 38
update delay
nCK
Read preamble
Read postamble
tCK (avg)
tRPST
0.3
0.3
tCK (avg)
Write preamble
tWPRE
tWPST
tWR
0.9
0.3
15
0.9
0.3
15
tCK (avg)
tCK (avg)
ns
1
Write postamble
Write recovery time
1
26
Auto precharge write recovery
WR + RU
WR + RU
tDAL
nCK
nCK
+ precharge time
(tRP/tCK (avg))
(tRP/tCK (avg))
Multi-Purpose register
recovery time
Read to write command delay
(BC4MRS, BC4OTF)
tMPRR
tRTW
tRTW
tWTR
tWTR
1
1
29
RL + tCCD/2
+ 2nCK − WL
RL + tCCD
+ 2nCK − WL
RL + tCCD/2
+ 2nCK − WL
RL + tCCD +
2nCK − WL
(BL8MRS, BL8OTF)
Internal write to read
command delay
18, 26,
27
18, 26,
7.5
7.5
ns
4
4
nCK
27
Internal read to precharge
command delay
tRTP
tRTP
tRAP
7.5
7.5
ns
26, 27
26, 27
28
4
4
nCK
Active to READ with auto
precharge command delay
tRCD min
tRCD min
Minimum CKE low width for self-
refresh entry to exit timing
tCKE (min.)
+1nCK
tCKE (min.)
+1nCK
tCKESR
Valid clock requirement after self-
refresh entry or power-down entry
tCKSRE
tCKSRE
tCKSRX
tCKSRX
10
5
10
5
ns
27
27
27
27
nCK
ns
Valid clock requirement before
self-refresh exit or power-down exit
10
5
10
5
nCK
Data Sheet E1375E50 (Ver. 5.0)
58
ELPIDA [ ELPIDA MEMORY ]
