EDE1108AFBG
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA
( 8 organization)
1
2
3
7
8
9
A
B
VDD NU/ /RDQS VSS
VSSQ /DQS VDDQ
DQS VSSQ DQ7
VDDQ DQ0 VDDQ
DQ2 VSSQ DQ5
DQ6 VSSQ DM/RDQS
C
D
VDDQ
DQ4 VSSQ DQ3
DQ1 VDDQ
E
F
G
H
J
VREF VSS
CKE /WE
VSSDL CK
VDD
ODT
VDDL
/RAS
/CAS
A2
/CK
/CS
A0
BA2
BA0
A10
BA1
A1
VDD
VSS
VSS
VDD
A3
A7
A5
A9
NC
A6
A11
NC
A4
A8
K
L
A12
A13
(Top view)
Pin name
A0 to A13
BA0, BA1, BA2
DQ0 to DQ7
DQS, /DQS
RDQS, /RDQS
/CS
Function
Pin name
Function
Address inputs
Bank select
ODT
VDD
VSS
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Data input/output
Differential data strobe
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*1
Differential data strobe for read
Chip select
/RAS, /CAS, /WE
CKE
Command input
Clock enable
CK, /CK
Differential clock input
Write data mask
DM
NU*2
Not usable
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
Preliminary Data Sheet E1430E20 (Ver. 2.0)
3
ELPIDA [ ELPIDA MEMORY ]
