EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Refresh Requirements
DDR2 SDRAM requires a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two
ways: by an explicit automatic refresh command, or by an internally timed event in self-refresh mode. Dividing the
number of device rows into the rolling 64 ms interval defines the average refresh interval, tREFI, which is a guideline
to controllers for distributed refresh timing.
Automatic Refresh Command [REF]
When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters the automatic
refresh mode (REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the precharge
time (tRP) before the auto-refresh command (REF) can be applied. An address counter, internal to the device,
supplies the bank address during the refresh cycle. No control of the external address bus is required once this
cycle has started.
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay
between the auto-refresh command (REF) and the next activate command or subsequent auto-refresh command
must be greater than or equal to the auto-refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of 8 refresh commands can be posted to any given DDR2 SDRAM, meaning that
the maximum absolute interval between any refresh command and the next Refresh command is 9 × tREFI.
T0
T1
T2
T3
/CK
CK
VIH
≥ tRP
≥ tRFC
≥ tRFC
CKE
Any
Command
PRE
NOP
REF
REF
NOP
Command
Automatic Refresh Command
Data Sheet E0852E50 (Ver. 5.0)
70
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