EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Self-Refresh Command [SELF]
The DDR2 SDRAM device has a built-in timer to accommodate self-refresh operation. The self-refresh command is
defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock.
ODT must be turned off before issuing self-refresh command, by either driving ODT pin low or using EMRS
command. Once the command is registered, CKE must be held low to keep the device in self-refresh mode.
When the DDR2 SDRAM has entered self-refresh mode all of the external signals except CKE, are “don’t care”.
The clock is internally disabled during self-refresh operation to save power. The user may change the external clock
frequency or halt the external clock one clock after Self-Refresh entry is registered, however, the clock must be
restarted and stable before the device can exit self-refresh operation. Once self-refresh exit command is registered,
a delay equal or longer than the tXSNR or tXSRD must be satisfied before a valid command can be issued to the
device. CKE must remain high for the entire self-refresh exit period tXSRD for proper operation. NOP or deselect
commands must be registered on each positive clock edge during the self-refresh exit interval. ODT should also be
turned off during tXSRD.
T0
T1
T2
T3
T4
T5
T6
Tm
Tn
tCK
tCH tCL
/CK
CK
≥ tXSNR
≥ tXSRD
tRP*
CKE
ODT
tIS
tIS
tAOFD
tIS
tIH
tIS
NOP
NOP
Valid
SELF
Comand
NOP
Notes: 1. Device must be in the “All banks idle” state prior to entering self refresh mode.
2. ODT must be turned off tAOFD before entering self refresh mode, and can be turned on again
when tXSRD timing is satisfied.
3. tXSRD is applied for a read or a read with autoprecharge command.
4. tXSNR is applied for any command except a read or a read with autoprecharge command.
Self-Refresh Command
Data Sheet E0852E50 (Ver. 5.0)
71
ELPIDA [ ELPIDA MEMORY ]
