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EDE1108ABSE-4A-E 参数 Datasheet PDF下载

EDE1108ABSE-4A-E图片预览
型号: EDE1108ABSE-4A-E
PDF下载: 下载PDF文件 查看货源
内容描述: 1G位DDR2 SDRAM [1G bits DDR2 SDRAM]
分类和应用: 存储内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 82 页 / 645 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EDE1104ABSE, EDE1108ABSE, EDE1116ABSE  
Power-Down [PDEN]  
Power-down is synchronously entered when CKE is registered low (along with NOP or deselect command). CKE is  
not allowed to go low while mode register or extended mode register command time, or read or write operation is in  
progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto-  
precharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those  
operations. Timing diagrams are shown in the following pages with details for entry into power-down.  
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting  
power-down mode for proper read operation.  
If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down  
occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down  
deactivates the input and output buffers, excluding CK, /CK, ODT and CKE. Also the DLL is disabled upon entering  
precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-  
down. In power-down mode, CKE low and a stable clock signal must be maintained at the inputs of the DDR2  
SDRAM, and ODT should be in a valid state but all other input signals are “Don’t Care”. CKE low must be  
maintained until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.  
The power-down state is synchronously exited when CKE is registered high (along with a NOP or deselect  
command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be  
applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes high. Power-down exit latency is  
defined at AC Characteristics table of this data sheet.  
CK  
/CK  
tIS tIH  
VALID  
tIS tIH  
NOP  
tIH  
tIS  
tIH  
tIS tIH  
VALID  
CKE  
VALID  
NOP  
VALID  
Command  
tCKE min  
tXP, tXARD,  
tXARDS  
tCKE min  
Enter power-down mode  
VIH or VIL  
Exit power-down mode  
Power-Down  
Read to Power-Down Entry  
T0  
T1  
T2  
Tx  
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9  
/CK  
CK  
Read operation starts with a read command and  
CKE should be kept high until the end of burst operation.  
Command  
READ  
VIH  
CKE  
DQS  
/DQS  
AL + CL  
out out out out  
DQ  
0
1
2
3
BL=4  
T0  
T1  
T2  
Tx  
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9  
CKE should be kept high until the end of burst operation.  
Command  
CKE  
READ  
VIH  
DQS  
/DQS  
AL+CL  
out out out out out out out out  
BL=8  
DQ  
0
1
2
3
4
5
6
7
Data Sheet E0852E50 (Ver. 5.0)  
72  
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