EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits BA0, BA1, A11 through A0
as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has five fields;
Option
: A11 through A9, A7
: A8
DLL reset
/CAS latency
Wrap type
Burst length
: A6 through A4
: A3
: A2 through A0
Following mode register programming, no command can be issued during tMRD.
/CAS Latency
/CAS latency is the critical parameter. It tells how many clocks must elapse before the data is available.
The value is determined by the frequency of the clock and the speed grade of the device.
Burst Length
Burst length is the number of words that will be output or input in read or write cycle. After read burst is completed,
the output bus becomes Hi-Z.
The burst length is programmable as 2, 4 and 8.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data is addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen depends on the type of CPU in the system.
Some microprocessor cache system are optimized for sequential addressing and others for interleaved addressing.
7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both
sequences support bursts of 2, 4 and 8.
The extended mode register has two fields;
Option
: A11 through A1
: A0
DLL enable
22
Preliminary Data Sheet E0136E30
ELPIDA [ ELPIDA MEMORY ]
