EDD1204ALTA, EDD1208ALTA, EDD1216ALTA
5. Initialization
The EDD12xxALTA is initialized in the power-on sequence according to the following.
(1) Power must first be applied to VDD, then VDDQ, and finally to VREF. VTT must be applied.
(2) Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS
output will be in Hi-Z state.
(3) To stabilize internal circuits, when power is applied a 100 µs or longer pause must precede any signal toggling.
(4) After the pause, all banks must be precharged using precharge command. The precharge all banks command is
convenient.
(5) EMRS command must be performed to enable or disable DLL. Then MRS command must be applied to reset
DLL. After this MRS command additional 200 cycles are required before read command.
(6) All banks must be precharged using precharge command again. Then two or more CBR (auto) refresh command
must be performed.
(7) After the refresh the mode register can be programmed by MRS command.
Case 1: MRS after the REF
Min. 200 cycles before Read command
t
MRD
t
MRD
tRP
t
RFC
t
RFC
tMRD
CLK
CKE
Any
Command
PALL
EMRS
MRS
PALL
REF
MRS
REF
Command
DLL reset
DLL
enable / disable
Minimum 2 REF cycles must be performed.
Remark Two refresh commands may be follow the first MRS command.
21
Preliminary Data Sheet E0136E30
ELPIDA [ ELPIDA MEMORY ]
