EBD52UC8AKDA
Pin Capacitance (TA = 25°C, VDD = 2.5V ± 0.2V)
Parameter
Symbol
CI1
Pins
max.
TBD
TBD
Unit
pF
Notes
Input capacitance
Input capacitance
Address, /RAS, /CAS, /WE
CK, /CK, CKE, /CS
CI2
pF
Data and DQS input/output
capacitance
CO
DQ, DQS, DM
TBD
pF
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Component Specification)
-6B
-7A
-7B
Parameter
Symbol
tCK
min.
max.
12
min.
max.
12
min.
max
12
Unit
Notes
10
Clock cycle time
(CL = 2)
7.5
7.5
10
ns
(CL = 2.5)
tCK
tCH
tCL
6
12
7.5
12
7.5
12
ns
CK high-level width
CK low-level width
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
min
min
min
CK half period
tHP
tAC
—
—
—
tCK
ns
(tCH, tCL)
(tCH, tCL)
(tCH, tCL)
DQ output access time from
CK, /CK
–0.7
0.7
–0.75
0.75
–0.75
0.75
2, 11
DQS output access time from CK,
tDQSCK –0.6
0.6
–0.75
—
0.75
0.5
–0.75
—
0.75
0.5
ns
ns
ns
ns
ns
2, 11
3
/CK
DQS to DQ skew
DQ/DQS output hold time from
DQS
Data hold skew factor
Data-out high-impedance time from
CK, /CK
tDQSQ
tQH
—
0.45
tHP – tQHS —
tHP – tQHS —
tHP – tQHS —
tQHS
tHZ
—
0.55
—
0.75
—
0.75
–0.7
0.7
0.7
–0.75
0.75
0.75
–0.75
0.75
0.75
5, 11
6, 11
Data-out low-impedance time from
CK, /CK
tLZ
–0.7
–0.75
–0.75
ns
Read preamble
tRPRE
tRPST
tDS
0.9
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
0.9
0.4
0.5
0.5
1.75
0
1.1
0.6
—
tCK
tCK
ns
Read postamble
0.4
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
0.45
0.45
1.75
0
8
8
7
tDH
—
—
—
ns
tDIPW
tWPRES
tWPRE
tWPST
—
—
—
ns
—
—
—
ns
0.25
0.4
—
0.25
0.4
—
0.25
0.4
—
tCK
tCK
Write postamble
0.6
0.6
0.6
9
Write command to first DQS
latching transition
DQS falling edge to CK setup time tDSS
DQS falling edge hold time from
CK
tDQSS
0.75
0.2
1.25
—
0.75
0.2
1.25
—
0.75
0.2
1.25
—
tCK
tCK
tCK
tDSH
0.2
—
0.2
—
0.2
—
DQS input high pulse width
tDQSH
tDQSL
0.35
0.35
—
—
0.35
0.35
—
—
0.35
0.35
—
—
tCK
tCK
DQS input low pulse width
Address and control input setup
time
Address and control input hold time tIH
Address and control input pulse
width
tIS
0.75
0.75
2.2
—
—
—
0.9
0.9
2.2
—
—
—
0.9
0.9
2.2
—
—
—
ns
ns
ns
8
8
7
tIPW
Preliminary Data Sheet E0367E20 (Ver. 2.0)
12
ELPIDA [ ELPIDA MEMORY ]
