EBD52UC8AKDA
Block Diagram
/CS1
/CS0
R
R
S
S
/CS
/CS
/CS
/CS
DQS0
DQS4
DQS
DM
DQS
DM
DQS
DM
DQS
DM
R
R
R
S
R
S
R
S
S
DM0
DM4
D0
D8
D4
D12
8
8
8
8
S
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
DQ0 to DQ7
DQ32 to DQ39
R
S
DQS1
DQS5
DQS
DM
DQS
DM
DQS
/CS
DQS
/CS
/CS
/CS
R
R
R
R
S
S
DM1
DM5
DM
DM
D5
D13
D1
D9
S
S
DQ8 to DQ15
DQ40 to DQ47
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
R
S
R
S
/CS
/CS
/CS
/CS
DQS2
DQS6
DQS
DQS
DQS
DQS
R
R
R
R
R
S
S
S
S
DM
DM
DM2
DM
DM
DM6
D6
D14
D2
D10
8
8
8
8
S
I/O0 to I/O7
I/O0 to I/O7
DQ16 to DQ23
I/O0 to I/O7
I/O0 to I/O7
DQ48 to DQ55
R
S
/CS
/CS
DQS3
DQS7
/CS
/CS
DQS
DM
DQS
DM
DQS
DQS
R
R
R
R
S
S
DM3
DM7
DM
DM
D3
D7
D15
D11
S
S
DQ24 to DQ31
DQ56 to DQ63
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
I/O0 to I/O7
Serial PD
SDA
SCL
SDA
SCL
SA0
SA1
SA2
A0
A1
A2
U0
BA0 to BA1
A0 to AN
/RAS
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D15)
SDRAMs (D0 to D7)
SDRAMs (D8 to D15)
WP
/CAS
/WE
CK0
CKE0
CKE1
8 loads
/CK0
CK1
8 loads
0 loads
VDDSPD
VREF
SPD
SDRAMs (D0 to D15)
/CK1
CK2
/CK2
VDD
SDRAMs (D0 to D15), VDD and VDDQ
Notes :
1. DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VDDID strap connections:
VSS
SDRAMs (D0 to D15), SPD
SDRAMs (D0 to D15), SPD
VDDID
Open
(for memory device VDD, VDDQ)
Strap out (open): VDD = VDDQ
* D0 to D15 : 256M bits DDR SDRAM
U0 : 2k bits EEPROM
Strap in (closed): VDD ≠ VDDQ
2. The SDA pull-up registor is reguired due to
the open-drain/open-collector output.
3. The SCL pull-up registor is recommended,
because of the normal SCL lime inactive
"high" state.
Rs : 22Ω
Preliminary Data Sheet E0367E20 (Ver. 2.0)
8
ELPIDA [ ELPIDA MEMORY ]
