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EBD52UC8AKDA-6B-E 参数 Datasheet PDF下载

EBD52UC8AKDA-6B-E图片预览
型号: EBD52UC8AKDA-6B-E
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM Module, 64MX64, 0.7ns, CMOS, SODIMM-200]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 19 页 / 224 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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EBD52UC8AKDA  
DC Characteristics 1 (TA = 0 to +70°C, VDD = 2.5V ± 0.2V, VSS = 0V)  
Parameter  
Symbol  
IDD0  
Grade  
max.  
Unit  
mA  
Test condition  
Notes  
1, 2, 9  
-6B  
-7A, -7B  
1320  
1200  
CKE VIH,  
tRC = tRC (min.)  
Operating current (ACTV-PRE)  
CKE VIH, BL = 4,  
Operating current  
(ACTV-READ-PRE)  
-6B  
-7A, -7B  
1560  
1440  
IDD1  
mA  
CL = 2.5,  
1, 2, 5  
tRC = tRC (min.)  
Idle power down standby current  
Floating idle standby current  
IDD2P  
IDD2F  
48  
560  
480  
mA  
mA  
CKE VIL  
CKE VIH, /CS VIH,  
DQ, DQS, DM = VREF  
4
-6B  
-7A, -7B  
4, 5  
-6B  
480  
400  
CKE VIH, /CS VIH,  
Quiet idle standby current  
IDD2Q  
IDD3P  
IDD3N  
IDD4R  
IDD4W  
IDD5  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
4, 10  
-7A, -7B  
DQ, DQS, DM = VREF  
Active power down  
standby current  
320  
CKE VIL  
3
-6B  
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
-6B  
-7A, -7B  
880  
800  
2080  
1840  
2080  
1840  
3200  
2800  
CKE VIH, /CS VIH  
tRAS = tRAS (max.)  
CKE VIH, BL = 2,  
CL = 2.5  
CKE VIH, BL = 2,  
CL = 2.5  
tRFC = tRFC (min.),  
Input VIL or VIH  
Active standby current  
3, 5, 6  
1, 2, 5, 6  
1, 2, 5, 6  
Operating current  
(Burst read operation)  
Operating current  
(Burst write operation)  
Auto refresh current  
Input VDD – 0.2 V  
Input 0.2 V  
Self refresh current  
IDD6  
48  
Operating current  
(4 banks interleaving)  
-6B  
-7A, -7B  
3240  
2800  
IDD7A  
BL = 4  
5, 6, 7  
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.  
2. One bank operation.  
3. One bank active.  
4. All banks idle.  
5. Command/Address transition once per one cycle.  
6. Data/Data mask transition twice per one cycle.  
7. 4 banks active. Only one bank is running at tRC = tRC (min.)  
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.  
9. Command/Address transition once every two clock cycles.  
10. Command/Address stable at VIH or VIL.  
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)  
Parameter  
Symbol  
ILI  
min.  
–32  
max.  
32  
Unit  
µA  
Test condition  
Notes  
Input leakage current  
Output leakage current  
Output high current  
Output low current  
VDD VIN VSS  
VDD VOUT VSS  
VOUT = 1.95V  
ILO  
–10  
10  
µA  
IOH  
IOL  
–15.2  
15.2  
mA  
mA  
1
1
VOUT = 0.35V  
Note: 1. DDR SDRAM component specification.  
Preliminary Data Sheet E0367E20 (Ver. 2.0)  
11  
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