欢迎访问ic37.com |
会员登录 免费注册
发布采购

EBD52UC8AKDA-6B-E 参数 Datasheet PDF下载

EBD52UC8AKDA-6B-E图片预览
型号: EBD52UC8AKDA-6B-E
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM Module, 64MX64, 0.7ns, CMOS, SODIMM-200]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 19 页 / 224 K
品牌: ELPIDA [ ELPIDA MEMORY ]
 浏览型号EBD52UC8AKDA-6B-E的Datasheet PDF文件第6页浏览型号EBD52UC8AKDA-6B-E的Datasheet PDF文件第7页浏览型号EBD52UC8AKDA-6B-E的Datasheet PDF文件第8页浏览型号EBD52UC8AKDA-6B-E的Datasheet PDF文件第9页浏览型号EBD52UC8AKDA-6B-E的Datasheet PDF文件第11页浏览型号EBD52UC8AKDA-6B-E的Datasheet PDF文件第12页浏览型号EBD52UC8AKDA-6B-E的Datasheet PDF文件第13页浏览型号EBD52UC8AKDA-6B-E的Datasheet PDF文件第14页  
EBD52UC8AKDA  
Electrical Specifications  
All voltages are referenced to VSS (GND).  
Absolute Maximum Ratings  
Parameter  
Symbol  
VT  
Value  
Unit  
Note  
Voltage on any pin relative to VSS  
Supply voltage relative to VSS  
Short circuit output current  
Power dissipation  
–1.0 to +3.6  
–1.0 to +3.6  
50  
V
VDD  
IO  
V
mA  
W
°C  
°C  
PD  
8
Operating ambient temperature  
Storage temperature  
TA  
0 to +70  
–55 to +125  
1
Tstg  
Note: DDR SDRAM component specification.  
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause  
permanent damage. The device is not meant to be operated under conditions outside the limits  
described in the operational section of this specification Exposure to Absolute Maximum Rating  
conditions for extended periods may affect device reliability.  
DC Operating Conditions (TA = 0 to +70°C) (DDR SDRAM Component Specification)  
Parameter  
Symbol  
VDD, VDDQ  
VSS  
Min  
Typ  
2.5  
0
Max  
2.7  
0
Unit  
V
Notes  
1
Supply voltage  
2.3  
0
V
Input reference voltage  
Termination voltage  
Input high voltage  
Input low voltage  
VREF  
0.49 × VDDQ  
VREF – 0.04  
VREF + 0.15  
–0.3  
0.50 × VDDQ 0.51 × VDDQ  
V
VTT  
VREF  
VREF + 0.04  
VDDQ + 0.3  
VREF – 0.15  
V
VIH (DC)  
VIL (DC)  
V
2
3
V
Input voltage level,  
VIN (DC)  
VIX (DC)  
VID (DC)  
–0.3  
VDDQ + 0.3  
V
V
V
4
CK and /CK inputs  
Input differential cross point  
voltage, CK and /CK inputs  
Input differential voltage,  
CK and /CK inputs  
0.5 × VDDQ 0.2V 0.5 × VDDQ  
0.36  
0.5 × VDDQ + 0.2V  
VDDQ + 0.6  
5, 6  
Notes: 1. VDDQ must be lower than or equal to VDD.  
2. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.  
3. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.  
4. VIN (DC) specifies the allowable DC execution of each differential input.  
5. VID (DC) specifies the input differential voltage required for switching.  
6. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V  
if measurement.  
Preliminary Data Sheet E0367E20 (Ver. 2.0)  
10  
 复制成功!