AC CHARACTERISTICS
Table 7: General AC Characteristics
PARAMETER
SYMBOL
UNITS
Data Rate
100kbps
Data Rate
12.5kbps
MIN
0.99
MAX
1.01
MIN
0.99
MAX
1.01
1MCK Frequency
f1MCK
CKDC
TCRF
TDR
MHz
%
1MCK Duty Cycle
40
60
10
40
60
10
1MCK Rise/Fall Time
ns
Transmitter Data Rate (1MCK = 1MHz)
99
101
125
12.4
10.2
12.6
15.6
kbps
Receiver Data Rate (1MCK = 1MHz)
(DATA = 50% BIT/ 50% NULL TIME)
Receiver Data Rate
RDR
83.3
kbps
/NFD
71.4
166
8.77
19.2
kbps
No Frequency Discrimination (/NFD=0)
AC TIMING CHARACTERISTICS
Table 8: 3V AC Characteristics
SYMBOL MIN
PARAMETER
TYP
MAX UNITS
CONTROL WORD TIMING
Pulse Width: /CWSTR tCWSTR
Setup: DATA BUS Valid to /CWSTR Hi tCWSET
Hold: /CWSTR Hi to DATA BUS Hi-Z tCWHLD
80
60
40
ns
ns
ns
RECEIVER FIFO AND LABEL READ TIMING
Delay: Start ARINC 32nd bit to /DR Lo:
High Speed
Low Speed
Delay: /DR Lo to /EN Lo
Delay: /EN Hi to /DR Hi
Setup: SEL to /EN Lo
Hold: SEL to /EN Hi
Delay: /EN Lo to DATA BUS Valid
Delay: /EN Hi to DATA BUS Hi-Z
Pulse Width: /EN1 or /EN2
Spacing: /EN Hi to next /EN Lo (Same ARINC Word)
Spacing: /EN Hi to next /EN Lo (Next ARINC Word)
tD/R
tD/R
16
128
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
tD/REN
tEND/R
tSELEN
tENSEL
tENDATA
tDATAEN
tEN
0
60
80
150
20
20
140
100
120
140
1033
tENEN
tREADEN
TRANSMITTER FIFO AND LABEL WRITE TIMING
Pulse Width: /PL1 or /PL2
tPL
tDWSET
tDWHLD
tPL12
tLABEL
tTX/R
80
60
40
40
60
ns
ns
ns
ns
ns
ns
Setup: DATA BUS Valid to/PL Hi
Hold: /PL Hi to DATA BUS Hi-Z
Spacing: /PL1 to /PL2
Spacing between Label Write pulses
Delay: /PL2 Hi to TX/R Lo
100
50
TRANSMISSION TIMING
Spacing: /PL2 Hi to ENTX Hi
Delay: 32nd ARINC Bit to TX/R Hi
Spacing: TX/R Hi to ENTX Lo
tPL2EN
tDTX/R
tENTX/R
0
0
ns
ns
ns
REPEATER OPERATION TIMING
Delay: /EN Lo to /PL Lo
Hold: /PL Hi to /EN Hi
Delay: TX/R Lo to ENTX Hi
MASTER RESET PULSE WIDTH
tENPL
tPLEN
tTX/REN
tMR
0
0
0
80
ns
ns
ns
ns
ARINC DATA RATE AND BIT TIMING
± 1%
Table 9: 5V AC Characteristics
©2015 Device Engineering Inc.
12 of 15
DS-MW-01084-02 Rev. H
11/24/2015
DEIAZ [ Device Engineering Incorporated ]
