BLOCK DIAGRAM
clk
reset
prgdatai(7:0)
prgdatao(7:0)
prgdataz
prgaddr(23:0)
prgrd
prgwr
xramdatai(7:0)
xramdatao(7:0)
xramdataz
xramaddr(23:0)
xramrd
xramwr
ramdatai(7:0)
ramdatao(7:0)
ramaddr(7:0)
ramoe
ramwe
sfrdatai(7:0)
sfrdatao(7:0)
sfraddr(7:0)
sfroe
sfrwe
docddatai
docddatao
docdclk
Opcode
Decoder
ALU
ramdatao[7:0]
ramaddr[7:0]
ramoe
ramwe
sfrdatao[7:0]
sfraddr[7:0]
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
output
Data bus for Internal Data Memory
Internal Data Memory address bus
Internal Data Memory output enable
Internal Data Memory write enable
Data bus for user SFRs
User SFRs address bus
User SFRs output enable
User SFRs write enable
Program Memory address bus
Output data bus for Program Memory
PRGDATA tri-state buffers control line
Program Memory read
Program Memory write
Data bus for External Data Memory
XDATA tri-state buffers control line
External Data Memory address bus
External Data Memory read
External Data Memory write
DoCD™ data output
DoCD™ clock line
Power management mode indicator
Stop mode indicator
Port 0 output
Port 1 output
Port 2 output
Port 3 output
Serial receiver output 0
Serial transmitter line 0
Serial receiver output 1
Serial transmitter line 1
Program
Memory
Interface
sfroe
Control Unit
sfrwe
prgaddr[23:0]
prgdatao[7:0]
External
Memory
Interface
Interrupt
Controller
int0
int1
prgdataz
prgrd
prgwr
xramdatao[7:0]
Internal Data
Memory
Interface
I/O Ports
User SFR
Interface
port0i(7:0)
port1i(7:0)
port2i(7:0)
port3i(7:0)
port0o(7:0)
port1o(7:0)
port2o(7:0)
port3o(7:0)
xramdataz
xramaddr[23:0]
xramrd
xramwr
docddatao
docdclk
pmm
stop
port0o[7:0]
port1o[7:0]
port2o[7:0]
port3o[7:0]
rxd0o
txd0
rxd1o
txd1
DoCD™
Debug Unit
Power
Management
Unit
stop
pmm
rxd0o
rxd0i
txd0
UART 0
Timers 0 & 1
t0
gate0
t1
gate1
PINS DESCRIPTION
PIN
clk
reset
ramdatai[7:0]
sfrdatai[7:0]
prgdatai[7:0]
xramdatai[7:0]
int0
int1
docddatai
port0i[7:0]
port1i[7:0]
port2i[7:0]
port3i[7:0]
t0
gate0
t1
gate1
rxd0i
TYPE
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
input
DESCRIPTION
Global clock
Global synchronous reset
Data bus from Internal Data Memory
Data bus from user SFRs
Input data bus from Program Memory
Data bus from External Data Memory
External interrupt 0 line
External interrupt 1 line
DoCD™ data input
Port 0 input
Port 1 input
Port 2 input
Port 3 input
Timer 0 clock line
Timer 0 clock line gate control
Timer 1 clock line
Timer 1 clock line gate control
Serial receiver input 0
UNITS SUMMARY
ALU
– Arithmetic Logic Unit performs the
arithmetic and logic operations during execu-
tion of an instruction. It contains accumulator
(ACC), Program Status Word (PSW), (B) regis-
ters and related logic such as arithmetic unit,
logic unit, multiplier and divider.
Opcode Decoder
– Performs an instruction
opcode decoding and the control functions for
all other blocks.
Control Unit
– Performs the core synchroniza-
tion and data flow control. This module is di-
rectly connected to Opcode Decoder and
manages execution of all microcontroller tasks.
Program Memory Interface
– Contains Pro-
gram Counter (PC) and related logic. It per-
forms the instructions code fetching. Program
Memory can be also written. This feature al-
lows usage of a small boot loader loading new
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Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
