●
Fully synthesizable, static synchronous de-
sign with positive edge clocking and no in-
ternal tri-states
●
Scan test ready
●
1.3 GHz virtual
clock frequency in a 0.35u
technological process
○
Read/write of single line and 8-bit group
●
Two 16-bit timer/counters
○
Timers clocked by internal source
○
Auto reload 8-bit timers
○
Externally gated event counters
●
Full-duplex serial port
PERIPHERALS
●
DoCD™ debug unit
○
Processor execution control
○
Run
○
Halt
○
Step into instruction
○
Skip instruction
○
Read-write all processor contents
○
Program Counter (PC)
○
Program Memory
○
Internal (direct) Data Memory
○
Special Function Registers (SFRs)
○
External Data Memory
○
Hardware execution breakpoints
○
Program Memory
○
Internal (direct) Data Memory
○
Special Function Registers (SFRs)
○
External Data Memory
○
Hardware breakpoints activated at a certain
○
Program address (PC)
○
Address by any write into memory
○
Address by any read from memory
○
Address by write into memory a required data
○
Address by read from memory a required data
○
Three wire communication interface
○
Synchronous mode, fixed baud rate
○
8-bit asynchronous mode, fixed baud rate
○
9-bit asynchronous mode, fixed baud rate
○
9-bit asynchronous mode, variable baud rate
CONFIGURATION
The following parameters of the DR80390 core
can be easy adjusted to requirements of dedi-
cated application and technology. Configura-
tion of the core can be prepared by effortless
changing appropriate constants in package file.
There is no need to change any parts of the
code.
•
Memory style
•
Program Memory type
•
Program Memory wait-
states
- Harward
- von Neumann
- synchronous
- asynchronous
- used (0-7)
- unused
- used
- unused
- synchronous
- asynchronous
- used (0-7)
- unused
-
subroutines
location
•
Program Memory writes
•
Internal Data Memory type
•
External Data Memory
wait-states
•
Interrupts
•
Power Management Mode
•
Stop mode
•
DoCD debug unit
●
Power Management Unit
○
Power management mode
○
Switchback feature
○
Stop mode
- used
- unused
- used
- unused
- used
- unused
●
Interrupt Controller
○
2 priority levels
○
2 external interrupt sources
○
3 interrupt sources from peripherals
Besides mentioned above parameters all
available peripherals and external interrupts
can be excluded from the core by changing
appropriate constants in package file.
●
Four 8-bit I/O Ports
○
Bit addressable data direction for each line
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Copyright 1999-2003 DCD – Digital Core Design. All Rights Reserved.
DCD [ DIGITAL CORE DESIGN ]
