Area
Component
[LC]
[FFs]
315
32
0
0
8
10
40
25
5
CPU*
1380
40
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR0 & DPTR1 auto-switch
Timed Access protection
Interrupt Controller
INT2-INT6
30
30
25
15
120
75
10
75
Power Management Unit
I/O ports
35
Timers
Timer 2
UART0
UART1
Master I2C Unit
Slave I2C Unit
SPI Unit
125
135
165
165
220
125
85
50
60
60
60
120
70
55
Compare Capture Unit
Watchdog Timer
Multiply Divide Unit 32
120
75
800
60
45
105
Total area
3815
1155
*CPU – consisted of ALU, Opcode Decoder, Control Unit, Program &
Internal & External Memory Interfaces, User SFRs Interface
Core components area utilization in STRATIX-II
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